If you are choosing a test strategy for a dense, low-volume, high-mix board and weighing bed-of-nails in-circuit test against JTAG boundary scan, here is the decision in one sentence: as physical access disappears and product mix climbs, the economics tip away from fixtures and toward boundary scan. In-circuit test is still excellent where you can reach the nodes and the volume justifies the tooling. The trouble is that fewer and fewer of today’s boards meet either condition. After thirty years of helping manufacturers make this call, these are the actual numbers and trade-offs I walk customers through.
What In-Circuit Test Actually Costs Before You Test a Single Board
The sticker price of an in-circuit tester is only the start. A bed-of-nails strategy carries a second cost that catches programs off guard: a custom fixture for every board variant. Each fixture is a machined plate drilled for hundreds or thousands of spring-loaded probes, wired to the tester, and debugged against a known-good board before it returns a trustworthy result.
That fixture is non-recurring engineering you pay up front, per product, before the first board is tested. On a high-mix line running dozens of variants, the fixture bill and the storage racks full of plates become the dominant cost — and every engineering change order that moves a test pad can mean re-drilling or rebuilding the plate. For low volumes, that cost is spread across very few boards, which is precisely where bed-of-nails stops making financial sense.
Where Bed-of-Nails Fixtures Run Out of Room
Cost aside, fixtures eventually hit a physical wall. A probe needs a pad to land on, and modern boards are deleting those pads. BGAs bury their connections, fine-pitch parts leave no room for a test point, and double-sided HDI layouts push accessible nodes below a usable fraction of the netlist. When access falls, fixture-based coverage falls with it, and you are left certifying a board on a fraction of its connections.
This is the same access problem that drives engineers toward boundary scan on no-access boards: the defects move to where the probes cannot go, so the test method has to follow them inside the silicon.
How JTAG Boundary Scan Changes the Access Equation
Boundary scan removes the fixture from the access problem entirely. The test access lives inside every IEEE 1149.1 compliant device, so the controller drives and senses pins through the chip’s boundary register rather than through a probe on a pad. A four-wire JTAG connection reaches interconnects a bed-of-nails plate could never touch, including the balls under a BGA.
The economics shift just as sharply. There is no per-variant fixture to machine. Re-targeting the test to a new board in a high-mix line is a software task — regenerate the vectors against the new netlist — not a mechanical rebuild. That is what makes boundary scan fit naturally with automated test on a high-mix assembly line, where the product changes faster than any fixture shop can keep up.
ICT vs. Boundary Scan: A Side-by-Side for High-Density Boards
For a low-volume, high-mix manufacturer weighing the two approaches, the trade-offs line up like this:
- Up-front tooling — ICT needs a custom fixture per variant; boundary scan needs only a JTAG connector and a vector set.
- Access on dense boards — ICT coverage falls as probe points disappear; boundary scan reaches buried BGA and fine-pitch interconnects directly.
- Changeover cost — a new ICT variant means a new plate; a new boundary scan target means regenerated software.
- Best fit — ICT rewards high volume with strong physical access; boundary scan rewards high mix, low volume, and shrinking access.
- Analog and bulk passives — ICT measures discrete component values directly; boundary scan targets digital interconnect, programming, and clustered logic.
That last line matters: the two methods are strong in different places, which is why the smartest answer is often not a contest between them.
You Do Not Have to Choose Just One
The most cost-effective strategy on a complex board is usually a layered one. Let boundary scan cover the digital interconnect, the BGA joints, the flash programming, and the clustered logic — everything access-bound — and reserve limited physical test for the analog and bulk-passive measurements only a probe can make. You get high coverage without paying for a fixture that tries, and fails, to reach everything.
Deciding where to draw that line is exactly the conversation in choosing the right JTAG test solution for your line, and our head-to-head on onTAP ProScan versus traditional test systems shows how the layered approach plays out on real boards.
Frequently Asked Questions
Is JTAG boundary scan cheaper than in-circuit test? For low-volume, high-mix production it usually is, because there is no custom fixture per board variant — the largest hidden cost of a bed-of-nails strategy. For very high volume with good probe access, ICT can still earn its tooling.
Can boundary scan fully replace a bed-of-nails fixture? On dense digital boards it replaces most of it. Where you still need analog or bulk-passive measurements, a hybrid strategy keeps a small amount of physical test alongside full boundary scan coverage.
How fast can I re-target boundary scan to a new board? Because the change is in software, a new program is generated against the new netlist rather than machined into a plate. Our FS-ATG test vector generation service turns a fault-graded program around in days.
Make the Call That Fits Your Mix
If your boards are dense, your volumes are modest, and your product mix keeps changing, the math rarely favors a rack of custom fixtures. Boundary scan moves test access into the silicon and changeover into software — the two things a high-mix line needs most. To see where your boards land, contact Flynn Systems for a coverage assessment, or review the full onTAP products and services line and the onTAP JTAG controllers that run the same program in engineering and on the floor.
0 Comments