When a board passes every test on the line and still fails in the field, the defect did not appear after shipment — it was there at test and nothing looked for it. That is the uncomfortable truth behind most warranty returns on digital assemblies: the escape is a gap in board-level fault coverage, not bad luck. A board is only proven on the nets your test actually exercises; everything else ships on hope. After thirty years of grading test programs for manufacturers, we have learned that the fastest way to lower an RMA rate is not more inspection at the end — it is measuring where your JTAG boundary scan coverage stops and closing the nets it never touched.
Why “Passed Test” and “Good Board” Are Not the Same Claim
A passing result means every test that ran, ran clean. It says nothing about the connections no test reached. On dense boards, the difference is large: opens under a BGA, a solder bridge on a fine-pitch bus, a mis-programmed flash device, or a broken interconnect between two buried parts can all sail through a test suite that simply never addressed those nets. The board leaves as a “pass” and returns as a field failure, and the two events are the same defect separated by weeks.
This is why coverage — not pass rate — is the number that predicts field reliability. A pass rate tells you how many boards cleared the tests you wrote. A coverage figure tells you how much of the board those tests were capable of proving in the first place. The same diagnostic reach that makes JTAG diagnostics pinpoint faults on the bench is what catches those defects before they ship.
Where the Escapes Hide on a Modern Assembly
Field failures cluster in the places physical test cannot see and untuned programs skip. Knowing where they hide is the first step to grading against them:
- BGA and no-access interconnect — joints buried under the package that a flying probe or bed-of-nails fixture can never land on, but a boundary scan chain drives directly.
- Fine-pitch shorts and opens — bridges and lifted pins on dense buses that inspection can miss and that only an electrical interconnect test confirms.
- Flash and configuration devices — a part that programmed incorrectly reads as present but behaves as failed once the product runs its firmware.
- Memory-cluster nets — address and data lines between a processor and its memory that need a functional cluster test, not just a continuity check.
- Untested “trusted” nets — connections assumed good because they always were, until a process drift or a component change makes them the next return.
Each of these is reachable through the IEEE 1149.1 boundary register, which is exactly what makes boundary scan the tool for shrinking the escape window. If the standard itself is new to your team, our primer on what boundary scan is and why your PCB needs it covers the fundamentals.
Measure Coverage Before You Try to Improve It
You cannot lower an escape rate you have never quantified. A fault-graded boundary scan program reports which nets and pins it proves and which it leaves untested, turning “we think the board is well tested” into a specific percentage and a specific list of gaps. That list is the work order: it names the nets a field failure is most likely to come from, so engineering effort goes where the risk actually is instead of being spread evenly across a board that is mostly already covered.
This is the measured, before-and-after approach behind our case study on a manufacturer that gained higher fault coverage with JTAG — the gains were not vague quality talk, they were named nets moved from untested to proven. Grading against the IEEE 1149.x standards every hardware engineer should know is what makes that number trustworthy rather than a guess.
The Return-Rate Math That Justifies the Test
The business case writes itself once coverage is visible. Every escape carries the full downstream cost — the return freight, the diagnosis, the repair or replacement, and the reputational drag of a customer who received a dead product. Catching that same defect at the test station costs seconds. Even a modest reduction in escape rate on a product with real field volume pays for the coverage work many times over, because you are trading a rare but very expensive event for a cheap and routine one. Higher fault coverage is not a quality expense; it is the lowest-cost place in the whole process to catch a defect.
Frequently Asked Questions
Does a high test pass rate mean my boards are reliable? Not on its own. A pass rate only reflects the tests you ran. Without a fault coverage figure showing how much of the board those tests could prove, a high pass rate can hide large untested areas that later become field returns.
How do I find out my current board-level fault coverage? A fault-graded boundary scan program reports covered versus uncovered nets and pins directly. That report converts an assumption about test quality into a measured percentage and a specific list of the gaps to close.
Can boundary scan catch defects that inspection and flying probe miss? Yes. Boundary scan reaches interconnects inside BGAs and other no-access nets that optical inspection and physical probes cannot, which is precisely where many field escapes originate.
Will improving coverage slow down my line? No. A boundary scan test runs in seconds through the JTAG chain, and catching a defect there is far faster and cheaper than processing the return it would otherwise become.
Turn Your Escape Rate Into a Coverage Number
Field returns are not random; they are the predictable output of nets your test never proved. Measuring boundary scan fault coverage turns that invisible risk into a list you can close, and closing it is the cheapest defect-catch in your entire process. To find out where your coverage stops, contact Flynn Systems for a fault coverage assessment of your board, have our FS-ATG test vector generation service grade a program against your netlist, or explore the full onTAP products and services line and the JTAG controllers that run the same coverage on the floor.
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