Vector Generation Service
Our Test Vector Generation Service provides accurate, reliable test vectors for PALs, GALs, CPLDs and FPGAs from well-known device manufacturers (Xilinx, Actel, Altera, Lattice, etc.). In most cases, you can expect results within 24 hours.
The FS-ATG Test Vector Generation Service includes:
Generation of package pin and/or internal node Stuck-At faults.
Detailed reports of the device performance, fault-scoring summaries, DFT information, state-transition information, logic analysis and edge-pin summary.
Test Vectors in your ATE Format
A sample of available output formats include:
- GenRad 228x/227x DTS
- GenRad 275x TGL
- HP 3065/3070 VCL
- HP 3065/3070 PCF
- Teradyne Z1800 ASC
- Teradyne Z8000 Z80
- Teradyne L Series SYM & CHA
- ViewLogic VL
- Altera VEC
- JEDEC JWV
How to get started
To get started, please send us your device source files and either tell us how the devices are constrained (pins connected/ignored), and tied to VCC/GND or send us the board netlist file (GenRad .CKT, HP board, or Teradyne IPL.DAT). FS-ATG software extracts that information automatically for each device on your board.
Send files via email to email@example.com
onTAP Turnkey Service
And Update Requests