What’s onTAP?

onTAP Series 4000 is a comprehensive, graphical, boundary scan tool providing users with a full suite of JTAG development and test tools. onTAP is designed and organized in a logical manner, reflecting the natural progression of tasks related to development and test. The notebook tab order of the screens helps to ensure the creation of thorough, accurate test solutions in a user-friendly environment.

How do I program programmable devices, such as ATMEL or Xilinx FPGAs or CPLDs, either directly through the JTAG chain or indirectly through a third device, like the memory bus of a JTAG compliant micro?

onTAP supports IN-SYSTEM CONFIGURATION of programmable devices via SVF files produced from: Xilinx ISE and iMPACT software, Altera Quartus, or Lattice development tools.  Utilization of onTAP’s Memory cluster Test Option (included in the evaluation version) is required for testing non-JTAG devices. The onTAP TAP CONNECT JTAG Controller should be used for large FPGAs.

Why is onTAP so affordable?

onTAP does not require expensive hardware to run. onTAP requires only the TAP CONNECT JTAG Controller, which is very affordable. The TAP CONNECT Controller is a dual-channel, high speed USB programming controller that allows multiple chain testing.

How do I perform real-time setting/clearing of a pin/node, allowing me to verify external circuits by probing and using the software user interface to set pin states?

onTAP’s ProScan visual control panel allows you to highlight any pin, along with all pins on its net. BS pins can be wiggled and test values captured and displayed.  Also, SAMPLE mode can be toggled on/off so that background application signal activity, such as clocks, can be observed.

What will I need to start?

How much time will I need to spend learning about onTAP?

onTAP requires considerably less time to learn than almost any other full-featured boundary scan product. In most instances, we can have you up and running a standard interconnect test within an hour.

What files are required?

A BSDL file for each JTAG compliant device is required to run any tests. A board netlist is also required to test any interconnect and cluster tests.

What hardware is required to use onTAP?

onTAP’s JTAG Controller is all you need to run tests and program FLASH memory devices. Capable of handling two chains, this device it has on-board, self-referencing VREF, as well as an internal VREF for boards that do not have power to the JTAG chain(s). The onTap JTAG Controller is also capable of Direct Drive Serial Flash Programming for SPI Flash and a low voltage version is also available.

What is a BSDL file?

A BSDL file is the Boundary Scan Description Language file, which is created by the manufacturer of the boundary scan device. The BSDL provides a necessary map of the device for anyone or anything trying to access the device. The file is usually provided with the device; however, this information can usually be found on most manufacturers websites.


Can onTAP support multiple JTAG chains?

Yes, and with onTAP support for multiple JTAG chains is simple and straightforward.  onTAP JTAG Controller can control two chains. Multiple onTap Controllers can be run from a powered USB hub.  Boundary scan pins are handled interactively between the chains, so that pins on one chain can transmit and receive to and from  pins on a different JTAG  chain. Bed-of-Nails

Do you have a library of BSDL devices?

No, primarily because there is no point, given the relative ease of obtaining BSDL files. We recommend that you always download and use the freshest, most current BSDL files by going directly to the device manufacturers’ website and downloading the BSDL file there. We are always available to assist in obtaining BSDL files if you should encounter a problem, though. Some proprietary devices do not have BSDL files available on a web site, but those files may be obtained through direct contact with the device manufacturer.

Is there a library of cluster test devices?

A sampling of library of models is available for many memory devices (e.g., SRAM, SDRAM, DDR4, DDR3, DDR2), as well as for programming and verification of many Flash devices (e.g., Spansion, Strataflash). If you let us know the device types you expect to be working with, we will gladly email you our corresponding models.

What other filename extensions can be used?

bsd, .bsdl, and .bsm


What is a netlist?

A netlist is simply a map of the Printed Circuit Board (PCB). It describes what devices are plugged into the board, and the specifics of the device types. For example, if your board has ten devices on it, and only four are JTAG devices, any boundary scan testware will need to know which devices are going to be tested, and which devices need to be transparent. The netlist provides that detailed information.

How do I import netlists?

onTAP reads over twenty netlist CAD formats (https://flynnsystems.com/2009/03/09/ontap-supported-netlist-readers-2/).  If you do not see your netlist format, contact our Tech Support (support@flynnsystems.com) and ask if a translator can be made

How do I quickly merge netlists from various sub-assemblies?

onTAP can merge two or more netlists, on a connector-to-connector basis, assuming corresponding pin numbers,  or on a pin-to-pin basis.  The merge procedure requires only a few minutes.

How does onTAP allow the automatic generation of short/open tests even when a single shorting link/resistor is in the netlist?

Automatic , netlist-based, test generation produces tests for opens, bus-wire, stuck-at, pull-up/pull-down, hard shorts, and mid-state shorts faults.  Low Ohm resistors, buffers, transceivers, and logic elements between boundary scan pins and between boundary scan and cluster-test-device pins are accounted for. Direction and enable pins on buffers and transceivers are dynamically managed.

How do I perform real-time probing/visualization of the state of observable pins/nodes in the netlist?

onTAP test programs can be run straight through on the Test screen where pin-level diagnostic messages are produced. In addition, the ProScan visual control panel provides program breakpoints to be set and test programs can be single-stepped so that conditions on a board can be probed and compared with expected values.






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