onTAP Download Request


Thank you for your continued interest in onTAP Series 4000 with support for IEEE 1149.1, IEEE 1149.6, and featuring enhanced automatic test generation for complex digital circuits.

  • All onTAP users with active software maintenance and 30-day evaluation licenses may download updates.
  • If your support contract is expired, please do not download the latest version of onTAP.
  • Updates are cumulative – we strongly advise keeping up with the latest builds.
  • For a complete listing of all software changes look in the onTAP online HELP section, “onTAP Change History.”
  • Please fill in the information in the form.
    Please click the button below to continue with the download.
  • Current build 4900.29 Updated April 19, 2024

“This [BLADE Network Research] is the second company I’ve used onTAP at, I’ve been using it for 3 or 4 years. Other vendors I’ve used tended to dismiss my problems or suggest a work around that just hides the problem. Lately I’ve been letting Flynn develop our applications because I just don’t have the time. That’s another option if you need a boundary scan test but have way too many other testing details to sort out.” F. Roberts ‘Test Engineer’ Blade Network Research

onTAP’s Enhanced, Highly Customizable TestPan Now Supporting Segmented Registers in the 2013 IEEE 1149.1 Std.

 onTAP Build Log

  • Corrects program exception that occurs in BSDL files having line lengths greater than 16K characters.
  • (Partial Suite Validated)
  • Improves consistency of USB Dongle licenses. The properties of the license_dongle_xx.lic file in the ‘C:\Flynn Systems Corp\onTAP’ folder should be set to Read Only. The onTAP _DLL_Demo has also been updated.
  • (Partial Suite Validated)
  • Includes additional edits for preliminary BNR syntax and semantics check of IEEE Std 1149.6 -2015 AIO Pin Behavior.
  • (Partial Suite Validated)
  • Includes preliminary BNR syntax and semantics check of IEEE Std 1149.6 -2015 AIO Pin Behavior.
  • (Partial Suite Validated)
  • Corrects management of Test screen Password Protection as controlled from License menu dialogue.
  • (Partial Suite Validated)
  • Adjusts handling of Secure Controller licensing
  • (Partial Suite Validated)
  •  Corrects crash condition when writing demo license requests when active license is dongle based
  • (Partial Suite Validated)
  • Upgrades BSDL port and boundary register cell syntax checking in compliance with IEEE 1149.1 2013 Para B.8.14.1.u.
  • (Partial Test Suite Validated)

Syntax checks that control cell numbers are in the boundary register range.

Syntax check that ports of type ‘inout’  have corresponding cell with control cells.

(Partial Suite Validated)


Adds option to include active signal switching for two-state buffer pins that do not have scannable receiver pins on their nets. This can be done by not selecting either of these two Interconnect Test Options on the TestGen pages’s TestPlan:

Use ‘0’ as default TDI don’t care bit value

Use ‘1’ as default TDI don’t care bit value

(Partial Suite Validated)


Fixes retention of No-Install settings

(Partial Suite Validated)


Maintains copied-settings between project tests after BSDL assignments are changed.

Corrects problem reading embedded dongle licenses

(Partial Test Suite Validated)


Improves fault coverage in resistive networks.

(Partial Test Suite Validated)


Corrects problem writing No-Install components on the Non-Scan page. This problem can cause the software to close and erase power and ground name settings.

(Partial Test Suite Validated)


Adjusts test generation to account for extended instances of in-line resistors.

(Partial Test Suite Validated)


Adds resizing and cursor placement to GetKeyboardString()  built-in DTS function.

(Partial Test Suite Validated)


Corrects and upgrades test generation for segmented register applications.

(Partial Test Suite Validated)


Improves BSDL file syntax error messaging

(Partial Test Suite Validated)


Corrects  BSDL file cell syntax checks for segmented registers

(Partial Test Suite Validated)


Corrects and upgrades syntax checking of BSDL files involving designation of control cells, use of LINKAGE bits, and case sensitivity of port names.

Build  4900.0-5 (Partial Suite Validated


Improves readability of diagnostic messages in BSDL file syntax checker

(Partial Test Suite Validated)


Corrects text in SVF file for REGISTER LENGTH MEASUREMENT when following a REGISTER SEGMENT INITIALIZATION TestPlan insert.

(Partial Test Suite Validated)


Upgrades syntax checking related to LINKAGE pin types.

(Partial Suite Validated)

4898.3Updates domain name to FlynnSystems.com

Updates to onTAP installer

Updates to BSDL syntax checking

(Partial Suite Validated)

4894- 4895Internal releases

Upgrades BSDL file syntax checker.

(Partial Test Suite Validated)


Upgrades BSDL file syntax checker for register  segments.

(Partial Suite Validated)


Upgrades insertion of PIO instructions into TestPlan.

(Partial Test Suite Validated)


Upgrades onTAP installer tool

(Partial Test Suite Validated)


Corrects problem checking BSDL file syntax for differential pair declarations.

(Partial Test Suite Validated)


Upgrades test generation for applications with multiple JTAG chains.

(Partial Test Suite Validated)


Corrects potential crash condition during test generation.

Restores TAP pins to top of Pins list in ProScan netlist browser.

(Partial Suite Validated)


Corrects problem with pull resistor tests

(Partial Suite Validated)


Corrects problem reading XNF netlists created using the  “Compose Netlist  Using BSDL File” tool when the project folder name ends with letters “ONTAP.”

(Partial Suite Validated)


Corrects crash related to BSDL file translation.

Corrects Test Generation problem involving PCA9306 bidirectional translators

(Partial Suite Validated)


Corrects crash related to BSDL file translation.

(Partial Suite Validated)


Corrects Test Generation problem involving PCA9306 bidirectional translators.

(Partial Suite Validated)


Corrects problem copying guards settings from one test to another.

(Partial Suite Validated)


Corrects and upgrades automatic test generation.

(Partial Suite Validated)

4875 4874 4873

Further upgrades BSDL syntax checking for opcodes and port_grouping syntax.

(Partial Suite Validated)


Upgrades BSDL syntax checker to verify port_grouping entities have a port assignment.

Corrects bug in jumpers list on jumpers page

(Partial Suite Validated)


Corrects test generation problem related to differential pair pins.

Corrects problem displaying pin names of jumpers on Jumpers page.

(Partial Suite Validated)


Updates Saleae-to-SVF translator to accept hexadecimal formatted input files.

Upgrades Test screen to handle SVF test files unlimited in size.

(Partial Suite Validated)


Corrects test generation problem involving pull resistors and models for small logic devices.

Upgrades handling of ferrite bead devices.

Removes requirement for imported SVF instructions to include TDO and MASK fields.

Edits logic model for PC*9306 device.

Corrects licensing problem for USB dongles with accompanying license file.

Adds translator to convert Saleae logic analyzer binary file scans to SVF files.

(Partial Suite Validated)


Corrects syntax checking of Reserved opcodes in BSDL files.

(Partial Suite Validated)


Corrects problem setting Test Logic Reset state in Chain C configurations.

(Partial Suite Validated)


Corrects crash conditions during test generation involving certain BSDL files.

(Partial Suite Validated)


Corrects problem on Cluster page where not all EXTERNALLY declared DTS  pins are shown in a multiple-JTAG chain application.

Corrects problem reporting syntax errors for JTAG cells that do not have corresponding port declarations in segmented register applications.

(Partial Suite Validated)


Upgrades BSDL syntax checking messages related to PIN_MAP_STRING declarations

(Partial Suite Validated)

4860 4861

Upgrades BSDL file syntax checking.

Upgrades automatic test generation and revises model for device PCA9306.

(Partial Suite Validated)


Corrects problem reading BSDL files that have formatting characters in text

(Partial Suite Validated)


Corrects TestGen problem involving low impedance resistors

(Partial Suite Validated)


Corrects potential TestGen problem involving guards settings

(Partial Suite Validated)


Upgrades automatic assignment of boundary scan pins to target cluster test device pins

(Partial Suite Validated)

Build 4855

Adds capability to drag and drop instructions within the TestGen page's TestPlan

(Partial Suite Validated)

Build 4854

Upgrades syntax checking for IEEE Std. 1149.1-2013. Use the onTAP menu item Tools / BSDL Syntax Check

(Partial Suite Validated)

Build 4853

Updates and improves test generation for differential pair circuits that are open.

(Partial Suite Validated)

Build 4852

Adds License menu  item to request a DEMO license.

(Partial Suite Validated)

Build 4851

Includes updates for test generation and fault scoring

When a test is run on the Test screen, test log files are copied to a Log Files subdirectory of the Test Reports folder or a folder specified in the Test/Test Settings menu dialogue

(Partial Suite Validated)

Build 4850

Restores register length measurement test which was inadvertently omitted in a prior build.

(Partial Suite Validated)

Build 4849

Corrects problem with IDCODE test introduced in previous build.

(Partial Suite Validated)

Build 4840- 4848

Continues test generation upgrades for complex circuits

(Partial Suite Validated)

Build  4839

Corrects operation for GPIO_2 channel

More  enhancements and corrections for non-JTAG circuits having multiple levels of transceivers and other logic devices.

(Partial Suite Validated)

Build 4836-4838Improves TestGen for circuits with complex non-JTAG components.
(Partial Test Suite Validated)

Build 4835Improves TestGen for circuits with multiple interacting transceiver buffers.
(Partial Test Suite Validated)
Build 4834Improves ProScan features and user prompts.
(Partial Test Suite Validated)
Build 4833Corrects test generation problem related to buffers permanently enabled on nets.
(Partial Test Suite Validated)
Build 4832Restores respective “include GPIO Netlist” setting on Projects page when reselecting a test.
(Partial Suite Validated)
Build 4831Removes restriction against parentheses characters in netlists
(Partial Test Suite Validated)

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Build 4830 4829 4828  4827Upgrades string variable assignment and concatenation operations in DTS cluster tests (Partial Suite Validated)
Build 4826Adjusts BSDL file parsing to account for multiple boundary register cells having the same cell number. (Partial Suite Validated)
Build 4825Upgrades automatic test generation and handling of non JTAG components such as transceivers. Upgrades ability to change administrative permissions so that an onTAP Development seat can be used for test-only purposes. (Partial Suit Validated)
Build 4824Allows SENSE_INPUT_HIGH guard on ground nets to test for some boundary scan cells that should be high although their related pin is connected to a ground net. A similar permission is available for power nets. Strips non-significant zero characters from package pin names in Mentor Neutral netlists.
Corrects update messages on TestGen page during test generation. (Partial Suite Validated)
Build 4823Adds a Generic Netlist Format netlist translator. See Input files in Help to view format style.
Corrects problem updating overall test suite status after programming a flash memory.
(Partial Suite Tested)
Build 4822Corrects problems and upgrades functional testing within interconnect tests using library truth-table models
(Partial Suite Tested)
Build 4821Automates procedure to set TCK clock rate for SVF files programming FPGAs.
(Partial Suite Tested)
Build 4820Corrects DTS program instruction problem specifying flash addresses in binary flash data files.
(Partial Test Suite Validated)
Build 4819

Adds functional test capability that can be combined with interconnect tests. Simply assign a logic model from the Logics.txt or LocalLogics.txt libraries and onTAP’s ATG will compile scans that test each line in a logic model’s truth table. This is distinct from project pin mapping which makes non-scan devices transparent to signals from scan pins during test generation.

Upgrades resistive shorts test, i.e., those connections through low impedance paths that are not detected and are not in a project’s netlist. Resistive shorts testing can be activated within interconnect tests and within ProScan.
Within interconnect tests choose the option ‘MID-STATE (resitive) Shorts Test’ on the Development screen’s TestGen Interconnect
Test Options.
In ProScan select ‘TRACE::resistive shorts’ in the Commands list.

Upgrades boundary register length measurement for applications having segmented boundary registers

Build 4818Upgrades test fault coverage when multiple receivers are configured on the N side of differential pair circuits.
(Partial Test Suite Validated)
Build 4817Corrects program exception on the Development screen involving large devices, i.e., over 4000 pins
(Partial Suite Validated)
Build 4816Corrects crash condition when the Examine SVF Tool item is selected
(Partial Test Suite Validated)
Build 4815Corrects problem with pull resistor tests in multi-chain configurations.
Expands on implementation of guards overrides to create functional tests, representing Logics models, within interconnect tests
(Partial Suite Validated)
Build 4814Corrects test vector number messaging error on the Test screen.
(Partial Test Suite Validated)
Build 4813Adds override controls for guards so that functional tests may be applied to scan pins in interconnect tests. See the discussion Placing Guards in a Table to Prescribe Test Generation in the Guards page context help.
Removes case sensitivity when parsing some PORT_GROUPING declarations in BSDL files.
Ensures that ShowFail and ShowPass instructions are properly executed in DTS cluster tests.
Adds alternate examine_svf file for specific customers
Build 4812Enhances syntax check in BSDL files for illegal characters in identifiers
(Partial Suite Validated)
Build 4811Corrects boundary register length syntax reporting error introduced in the build 4810.
(Partial Test Suite Validated)
Build 4810Corrects crash in applications having segmented registers and BSDL syntax errors related to entity declarations.
Adds new syntax checking for BSDL files.
(Partial Suite Validated)
Build 4809Corrects problem reading line lengths longer than 8K characters in BSDL files
(Partial Suite Validated)
Build 4808Corrects operation of the onTAP USB Controller test on the Test screen.
(Partial Suite Validated)
Build 4807Corrects problem handling some test values in multiple JTAG chain applications
(Partial Test Suite Validated)
Build 4806Corrects problem with onTAP DLL embedded dongle licensing.
(Partial Test Suite Validated)
Build 4805Updates Test screen so that selected SVF are executed on first click of Go button after initially loading project files. This removes requirement to double click after first load.
Corrects condition when using the Run Test on This File Only right-click menu item. The problem was that after using this menu item the first test was not run amongst selected tests when running a full test suite.
(Partial Suite Validated)
Build 4804Adds return values for the MESSAGE_PAUSE instruction when the YES_NO_CANCEL directive is used. These include ID_YES, ID_NO, and ID_CANCEL. ID_YES has a value of 1 and ID_NO has a value of 0 to preserve compatibility with existing DTS models, however ID_CANCEL has a numeric value of 2 so users should check usage in existing DTS code.
Fixes problem with the "Run Test on This File Only" menu option on the Test screen.
(Partial Suite Validated)
Build 4802Upgrades JAM player so that JAM files may be inserted in the SVF playlist on the Test screen and specified to erase, program, or verify. To erase a flash using JAM, prepend “erase_” to the JAM file name. To program prepend the text “program_” and to verify prepend “verify_”. As long as these files are present in a project folder they will appear and be selectable in the SVF playlist. JAM files must have a filename extension of “.jam”;
Corrects problem where test values were expected for differential pair receivers when the receivers had no direct UUT connection to related differential transmitters.
Corrects problem where SENSE_INPUT guards prevented cluster tests from working.
(Partial Test Suite Validated)
Build 4801Adds netlist translator for netlist files having BEGIN_COMPPROPS and BEGIN_NETS identifiers.
Build 4800Upgrades and corrects test generation to improve fault coverage in shared-control cell circuits.
(Partial Suite Validated)
Build 4799Boosts fault coverage for circuits having shared tri-state control cells.
(Partial Test Suite Validated)
Build 4798Upgrades TestGen algorithm producing higher fault coverage.
(Partial Suite Validated)
Build 4796Corrections for Test screen diagnostic messages.
Restores register assembly configuration to that prior to build 4794
(Partial Test Suite Validated)
Build 4794Corrects assembly error for segmented boundary register application.
(Partial Test Suite Validated)
Build 4793

Corrects problem with EXTERNAL pin assignments to multiple JTAG devices in Cluster tests.

Corrects problem with GetSubString cluster test function.

(Partial Test Suite Validated)

Build 4791Corrects problem where pressing space-bar can cause a cluster test to exit.
(Partial Test Suite Validated)
Build 4790Corrects parsing of EXTERNAL pins declarations in DTS models.
Improves status reporting error for OL/OH pin test statements in DTS cluster tests.
(Partial Test Suite Validated)
Build 4789Corrects error parsing bit_vector indices in BSDL files.
(Partial Suite Validated)
Build 4788Improves handling diagnostic messages for cluster tests when serial number entries are used on the Test screen.
(Partial Test Suite Validated)
Build 4787Corrects problem in Cluster tests when assigning DTS header pins directly to a boundary scan pin using the EXTERNAL pins declaration.
Adds warning messages and safeguards to the Boundary Register Length Test in the TAP test.
(Partial Test Suite Validated)
Build 4786Improves syntax checking of BSDL files. Adds additional syntax checks for IEEE Std_1149_1_2013 BSDL files when accessed from onTAP’s Tools/BSDL Syntax Check menu item.
(Partial Test Suite Validated)
Build 4785Corrects problems related to cluster test diagnostics introduced in the previous build.
(Partial Test Suite Validated)
Build 4784Adds additional corrections related to cluster testing in multiple JTAG chains
(Partial Test Suite Validated)
Build 4782Corrects problems with multichain cluster testing related to assigning variable values to pin groups.
Improves checking syntax in IEEE 1149.1 2013 specification BSDL files.
(Partial Test Suite Validated)
Build 4781Corrects test generation problems related to collapsing nets where bidirectional scan pins have common control cells.
(Partial Tests Suite Validated)
Build 4780Modifies onTAP DLL to facilitate GetLicenseInfo Instructions call from National Instruments LabVIEW.
(Partial Test Suite Validated)
Build 4778Adds PlayRecord procedure to buffer and speed up execution of pin-write instructions in .DTS cluster tests.
Build 4777Adds netlist converter for VayoPro-Test Expert format
(Partial Suite Validated)
Build 4776Corrects problem generating test solutions on the negative side of differential pairs when connecting receive pins to transmit pins using jumpers.
(Partial Test Suite Validated)
Build 4775Upgrades the PlayRecord option to speed up Flash programming when using DTS cluster tests.
(Partial Test Suite Validated)
Build 4774Adds netlist translator for OrCAD PCB II netlist format
Adjusts netlist translator for Protel 2 netlist formats
(Partial Test Suite Validated)
Build 4773Adds capability to include JAM programming files in the Test screen’s test suite so that the JAM/STAPL player is loaded automatically and runs JAM files without user intervention.(Partial Test Suite Validated)
Build 4772Adds syntax check, available in the Edit Register Segments tool, for Domain Control assignments in segmented registers.
Speeds up programming times in onTAP’s JAM / STAPL player
(Partial Test Suite Validated)
Build 4771Corrects IDCODE test problem encountered with Xilinx Zynq devices.
Changes the Opens test so that only half of the boundary registers pins are in the same state, high or low, at the same time.
(Partial Test Suite Validated)
Build 4770Adds JAM / STAPL player, available from onTAP’s Tools menu, for in-system programming and running JAM / STAPLfiles.
(Partial Test Suite Validated)
Build 4769Adjusts code to handle JTAG chain definition for Xilinx Zynq chips.
(Partial Test Suite Validated)
Build 4768Corrects problem setting tri-state condition (ID) in cluster tests for data bus pins having common control cells shared with differential pair clock strobes.
(Partial Test Suite Validated)
Build 4767Facilitates reading diagnostic messages when running multiple SVF files on the Test screen. Click on an SVF test filename to have any diagnostic messages rewritten.
(Partial Test Suite Validated)
Build 4766Improves diagnostic messages by including all pins involved in a test solution to diagnostic messages.
(Partial Test Suite Validated)
Build 4765Adds capability to pass arguments to the onTAP DLL when a test executive calls the onTAP DLLs RunSvfFile function.
Adds Get/Set functions to get and set variable’s values between test executives running onTAP DLLs and onTAP cluster tests. These functions include GetInt(), GetStr(), SetInt(), SetStr().
(Partial Test Suite Validated)
Build 4764Updates cell counts for changing segmented register assembly configurations in the Edit Register Assembly tool.
(Partial Test Suite Validated)
Build 4762Corrects problem parsing BSDL files related to segmented registers.
(Partial Test Suite Validated)
Build 4761Corrects uneven behavior of JTAG Controller self-test on the Test screen.
(Partial Test Suite Validated)
Build 4759On the Non-Scan page, added search tools below the Library Models list and the User’s non-JTAGs list.
(Partial Test Suite Validated)
Build 4758Corrects problem that occurs after multiple compiles of the same test and relating to differential pairs having LP_time and HP_time pin attributes.
(Partial Test Suite Validated)
Build 4757Corrects problem showing scandata for SIR instructions following an IDCODE instruction.
(Partial Test Suite Validated)
Build 4756Supports LP_time and HP_time attributes for 1149.6 AC testing.
Disables mutual enabling of scandata logging and the ShowMe! debug tool.
(Partial Suite Validated)
Build 4754Upgrades DTS Models Library selector on the Development screens Cluster page.
(Partial Test Suite Validated)
Build 4753If “Register Length Test” is selected in the “Register Segment Initialization” TestPlan group, then a full register length measurement is completed following the register segment initialization scans.
(Partial Test Suite Validated)
Build 4752Corrects summary fault score for shorts faults.
Ensures that Protel 2 netlist translator includes capacitors.
(Partial Test Suite Validated)
Build 4751Corrects operation of StepOn/StepOff instructions in Cluster tests.
(Partial Test Suite Validated)
Build 4750Updates syntax checking of cell types in BSDL files.
Corrects case sensitivity in parsing BSDL files so that parsing is not case sensitive.
(Partial Suite Validated)
Build 4749Corrects licensing problem when an onTAP license is embedded in a JTAG controller and opened on a computer which previously did not have an embedded JTAG controller license.
Upgrades procedure to update licenses embedded in USB JTAG controllers.
(Partial Suite Validated)
Build 4748Corrects problem showing IDCODE test results when a test is loaded.
Ensures that AC tests for capacitively coupled differential circuits are not enabled for DC cells.
Indicates a test failure if expected boundary register length does not match measured value.
Ensures that tests are not enabled for differential receivers when a circuit path between transmit and receive pins does not exist in the test solution’s netlist.
(Partial Suite Validated)
Build 4747Fixes problem related to parsing some BSDL files and reading the last port entry correctly.
Ensures that AC tests are not run on DC cells when capacitors are in test signal path.
Corrects problem that occurs when scandata logging is enabled and that shows null measured data for instruction capture values following the following IDCODE test.
Corrects diagnostic error reporting when an error occurs on a net but doesn’t resolve to an open, short, or stuck-at fault.
(Partial Suite Validated)
Build 4746Corrects problem managing TDR instructions in SVF files for FLASH programming.
(Partial Suite Validated)
Build 4745Adds SVF TAPMAP instruction following DTS ScanIR and ScanDR instructions to account for JTAG chain switching in multiple JTAG chain applications.
(Partial Suite Validated)
Build 4744Corrects PASS/FAIL message when the boundary register length measurement test does not match the expected value.
Corrects problem related to SIR scans when the MSB of a vector scan having an integral number of scan bytes is a logical one.
Corrects a duplicate message when programming flash devices.
(Partial Suite Validated)
Build 4743

Adds JTAG Reggie utility to Tools menu. Configures and runs Boundary Register settings including those for segmented registers. Settings are incorporated into SVF files which may be used in onTAP TestPlans.

Ensures that devices tagged as no-install do not appear in diagnostic messages
(Partial Suite Validated)

Build 4742Enable pin-wiggling control in ProScan for multiple-chain tests when Development screen is not open.
(Partial Suite Validated)
Build 4741Enable pin-wiggling control in ProScan for multiple-chain cluster tests.
(Partial Suite Validated)
Build 4740Corrects problem reading BSDL file syntax when colon character following PHYSICAL_PIN_MAP text is not followed by a space char.
(Partial Suite Validated)
Build 4739 
Build 4738Corrects polarity problem involving differential transmitters on different JTAG chains than differential receivers
(Partial Test Suite Validated)
Build 4737Corrects writing adaptor files for JTAG controllers when direct drive GPIO channels are assigned in DTS cluster test files.
(Partial Suite Validated)
Build 4736Corrects problem assigning TAPMAP instructions in multi-chain cluster test applications.
(Partial Test Suite Validated)
Build 4735Corrects handling of debug scandata and adjusts code involving wait instruction and .test file for Intel SVF format.
(Partial Suite Validated)
Build 4734Corrects inadvertent rewriting of controller adaptor files when a second controller is added.
Corrects declaration of wait instruction format in SVF files when the Intel formatting option is selected.
Writes a .test file when the Intel formatting option is selected.
(Partial Suite Validated)
Build 4733Ensures that IDCODES are reported when using LOG TDO HEX scandata and when the IDCODE test is preceded by a failing TAP test.
(Partial Suite Validated)
4732Restores TAPMAP line in SVF files for Intel SVF Format option in TestPlan (TestGen page)
Adds PRELOAD_SAFE instruction which can be inserted into TestPlan on TestGen page and which preloads safe values into all boundary register cells.
(Partial Suite Validated)
Build 4731Adds links on onTAP’s home screen to tutorial videos.
Reports measured boundary register length test data in scandata files.
Reports measured data in scandata files for SVF scans having null masks.
(Partial Suite Validated)
Build 4730Added support for the ODP++ netlist format in dot net files.
(Partial Test Suite Validated)
Build 4729Improved and cleaned up Test screen operation including code related to use of scandata debug option.
Fixed crash condition in ProScan when screen format style was changed.
(Partial Test Suite Validated)
Build 4727Corrects program crash condition during test generation..
Added capability to compare CSV output files from the Saleae JTAG protocol analyzer. See Debug menu item Saleae and Scandata Debug.
(Partial Suite Validated)
Build 4726Corrects handling of bit vectors in differential-pair pin groups
(Partial Test Suite Validated)
Build 4725Corrects differential-pair processing problem introduced in build 4721
(Partial Suite Validated)
Build 4724Corrects Boundary Register Length message on Test screen.
Corrects SVF when State Reset is deselected in the Test Plan and SAMPLE/PRELOAD is selected.
(Partial Suite Validated)
Build 4722Adjusts labels in SVF files to facilitate custom third party syntax preferences.
Ensures custom SVF-syntax files run on the Test screen.
(Partial Suite Validated)
Build 4721Revises formatting in SVF files for multi-chain applications.
Revamps diagnostic messages in SVF files for multi-chain applications.
Adds customized diagnostic message labels in SVF files for Intel Corp.
Upgrades BSDL file parsing to improve support for IEEE 1149.x-2013 and segmented registers.
Adds button controls to select or deselect all files in the Deploy menu item control.
(Partial Suite Validated)
Build 4720Corrects problem reading BSDL files introduced in previous build.
Build 4719Ensures unique test vector text for each test vector in SVF files.
Corrects program exception problem when reading some Intel BSDL files.
(Partial Test Suite Validated)
Build 4718Posts TAP test results on Test screen when loading SVF test files. Includes JTAG chain order as well as expected and measured IDCODE values.
Automatically edits JTAG adaptor files when JTAG controllers are changed.
Ensures that a PASS test result is not posted when selected SVF files with a status of “not tested” exist.
(Partial Suite Validated)
Build 4717Ensures that test values for self-monitoring cells ac_9, bc_9, ac_10 and bc_10 are included in tests.
(Partial Test Suite Validated)
Build 4715Removes redundant SVF file instruction and data scans during test execution so that logic analyzer protocol analysis of TDO and TDI data corresponds one-to-one with SVF file instructions.
(Partial Suite Validated)
Build 4714Ensures that boundary register tests are not run on the first EXTEST vector when the PRELOAD option is not enabled
(Not Full Suite Validated)
Build 4713Updates “Copy Settings” to include Register Segment Assembly settings.
Corrects crash condition involving PIO instructions.
Not Full Suite Validated)
Build 4712Corrects IDCODE test problem created by previous release.
(Not Full Suite Validated)
Build 4711Corrects problem with GPIO instructions inserted in TestPlan
Corrects problem showing 0-1-L-H option in ProScan.
Adjusts register assembly order for segmented boundary registers.
(Not Full Test Suite Validated)
Build 4710In TestPlan, automates insertion of setup scan for register segments as specified in IEEE 1149.1-2013.
Upgrades “Edit Register Segments” control panel accessible from Menu/Tools.
(Not Full Suite Validated)
Build 4709Upgrades Segment Register Edit tool and adds controls to reset segment register configuration or include all register segments.
Build 4708Corrects problem reporting Register Length Test.results.
(Not Full Test Suite Validated)
Build 4707Adds Interconnect and Cluster Test instructions to t he Instructions list on the TestGen page, allowing multiple interconnect, as well as Cluster tests, in one TestPlan.
Corrects problem asserting a string of TAP STATE instructions
Build 4706Corrects problem presenting pin lists in ProScan.
Corrects problem with implementation of TAP TRANSITION path options in TestGen.
(Not Full Test Suite Validated)
Build 4705Improves fault coverage for IEEE Std 1149.6 differential pair circuits.
Improves performance in ProScan for very high pin count devices.
(Not Full Test Suite Validated)
Build 4704Adds support for segmented registers in the IEEE Std 1149.1-2013 specification.
Adjusts presentation on Test screen of IDCODE messages.
(Not Full Test Suite Validated)
Build 4703Allows hyphenated MAC address entry on License dialogue, P/W Settings
Default options setting for “Control File for Multiple UUTs” on TestGen page is deselected.
(Not Full Test Suite Validated)
Build 4702Ensures that all pins on collapsed nets are included in diagnostic messages.
Restores measured IDCODE values in test messages.
(Not Full Test Suite Validated)
Build 4700Corrects problem propagating SENSE guard to multiple scan pins connected by a resistor network.
(Not Full Test Suite Validated)
Build 4699Adjusts test generation to ensure that all scan pins connected through resistor networks are included in test solutions.
Corrects problem involving test generation when some devices in a JTAG chain are placed in BYPASS or HIGHZ mode.
Adjusts manager privileges on Test screen to allow changing test selections.
Corrects problem saving/restoring test settings related to the time stamp option.
(Not Full Suite Validated)
Build 4696Adds administrative privileges and access control on the Test screen.
Contact Flynn Systems Tech Support for procedure to add admin passwords.
(Not Full Test Suite Validated)
Build 4695 
Build 4693Adds drop down menu for Test screen Operator selection.
Adds SetSerialNumber() DTS instruction.
Adds password-protected procedure to lock SVF settings on the Test screen.
(Not Full Test Suite Validated)
Build 4691Corrects test generation problem involving differential pairs.
(Not Full Suite Validated)
Build 4690Adds alternate version of GetSubStr() instruction that returns substring based on a starting character position and prescribed text extent.
Adds summary test log when running a suite of tests on Test screen, if a a Unit Type entry is made.
Adds option to lock SVF selections on Test screen.
Adds SVF Version option to Test Plan on TestGen page.
(Not Full Suite Validated)
Build 4689On the Test screen, consolidates Go / Stop functions into the Go button.
Corrects problem reading Genum BSDL files.
Build 4688On the Test screen, consolidates Go / Stop functions into the Go button.
Corrects problem reading Genum BSDL files.
(Not Full Test Suite Validated)
Build 4687Corrects problem involving incorrect test values following a pull-up/pull-down resistor test.
Build 4686Corrected problem where the same MESSAGE_PAUSE instructions were presented twice
(Not Full Test Suite Validated)
Build 4684Corrects program exception when reading a Genum BSDL file.
(Not Full Suite Validated)
Build 4683Ensures that pins, connected resistively to nets assigned as Vref , are not driven but are tested to be at a logic one level
(Not Full Suite Validated)
Build 4681Updates onTAP test generation for cluster test parallel test conditions as well as differential pairs test generation.
(Not Full Test Suite Validated)
Build 4679Corrects problem implementing DTS file’s .PARALLEL instruction, used to control cluster testing multiple devices in parallel.
(Not Full Test Suite Validated)
Build 4677Upgrades STOP FURTHER TESTING ON FAIL option on Test screen.
(Not Full Test Suite Validated)
Build 4676Adjusts diagnostics for Scan Bridge applications.
Corrects handling of EXTEST_TOGGLE instruction on TestGen page.
Adjusts handling of MESSAGE_PAUSE so a ‘?’ will prompt a response/
(Not Full Suite Validated)
Build 4674Corrects test generation problem involving the .PARALLEL directive in DTS cluster test models.
Adds capability on the TestGen page to insert pad bits for SCANSTA scan bridge applications. Corrects test generation problem involving bidirectional buffers.
Ensures that invert-capture-value guards affect only signals received from a pin other than the pin to which the guard is assigned.
Adds Register Length Test to TAP Test options in TestPlan. Provides test and length of registers indicated by opcode selections. (For existing test plans, select Restore Default Settings to enable this option.)
Grays out and disables user controls on Test screen while a test is running.
Adjusts MESSAGE_PAUSE instruction so that a ‘?’ in text does not cause YES/NO buttons to be presented.
Added right-menu item on Test screen to sort SVF files list.
(Not Full Test Suite Validated)
Build 4673Adds convenience search tool on Scan page to search Device names and also a right-click menu selection to move Device names to the top of the Devices list.
(Not Full Test Suite Validated)
Build 4672Corrects crash condition related to long file path names.
(Not Full Test Suite Validated)
Build 4671Added new Test screen option that allows test reports to be copied to a specified folder. See Test Reports Folder in the Options dialogue.
Corrects operation of the ‘Run Test on this File Only” menu (right click) selection on the Test screen.
Corrects handling of OUTPUTS_OFF_INPUTS_OFF guard so that pull down resistor tests are not run on input-only pins.
Adjusts reordering of SVF files on Test screen so that reordered files can be run in adjusted sequence without closing and reopening test project.
Adds menu option to run selected SVF files starting from a selected file.
Corrects handling of SVF scans within DTS model files.
Corrects problem when the text “_check” is used in a DTS name.
(Not Full Suite Validated)
Build 4670Adds Test screen option to log all test messages to a test_screen_messages.txt file.
(Not Full Test Suite Validated)
Build 4669Corrects problem generating test solution for AC differential circuits when multiple circuit elements are in series with coupling capacitors.
(Not Full Test Suite Validated)
Build 4668Generalizes capability to mix DTS cluster test instructions and GPIO instructions using TAP pins.
(Not Full Test Suite Validated)
Build 4667Corrects assignment of cluster test pins to scan pin for differential clocks.
(Not Full Suite Validated)
Build 4666Copies ‘.fail’ file to Test Reports folder when “Copy reports to Test Reports subdirectory” is selected.
Changes the STOP FURTHER TESTING ON FAIL option for the Test screen’s pop-up menu in the SVF files list. This option is now restricted only to SVF files that are selected in the list.
(Not Full Test Suite Validated)
Build 4665Updates Help documents.
Removes option to strip leading ‘0’ characters from BSDL pin names.
(Not Full Test Suite Validated)
Build 4664Adds string array capability to DTS cluster test scripting.
Corrects handling of alternate IDCODES
Fixes potential crash condition related to pull resistor tests.
Builds 4659-4663 dealt with internal changes.
(Not Full Test Suite Validated)
Build 4658Corrects problem writing MESSAGE instructions for 64 bit integers
(Not Full Test Suite Validated)
Build 4657Upgrades IEEE 1149.6 AC test generation
(Not Full Test Suite Validated)
Build 4655Upgrades IEEE 1149.6 AC tests involving ‘in’ pins on nets also having ‘buffer type pins.
(Not Full Test Suite Validated)
Build 4654Upgrades automatic test generation’s handling of non-boundary scan circuits.
(Not Full Test Suite Validated)
Build 4653Ensures logic one test for open collector nets driven by weak1 bidirectional cells.
(Not Full Test Suite Validated)
Build 4651Adds messaging construction in DTS models that facilitates accessing net names and net pins for individual pins within a pin group; Reference %NET in onTAP Help’s DTS Programming Format document
(Not Full Test Suite Validated)
Build 4650Adjusts background colors on the Test screen so that passing SVF files are shown with a green tint, failing files with a red tint and non-tested files with a gray-blue tint.
(Not Full Test Suite Validated)
Build 4648Adjusts controls and messages on the Test screen. Right clicking in the Test Status column shows the diagnostic message if it exists for the related SVF file.
Build 4647Ensures that the Test screen’s FAIL image is posted if any SVF files fail in a test suite when multiple SVF files are selected.
Tints failing lines red in the Test screen’s SVF list.
Updates rules to view failing diagnostic messages when multiple SVF files are checked. Either click in the Test Status column of a particular SVF and then lick View Fails or right click on an SVF file name and then select View Last Diagnostic Message.
Note that clicking directly on an SVF file name will bring up user prompt messages and also run a TAP test that shows IDCODES.
(Not Full Test Suite Validated)
Build 4643Corrects handling of manually generated jumper files.
(Not Full Suite Validated)
Build 4642Corrects potential hang condition in ProScan.
Removes Guards Wizard functions from the Development screen’s Guards page since the Wizard’s essential functionality is now part of ProScan.
(Not Full Suite Validated)
Build 4641Includes changes related to the Installer program.
(Not Full Test Suite Validated)
Build 4640Additional corrections for differential networks that have non-differential I/O pins on the differential nets.
(Not Full Test Suite Validated)
Build 4639Adjusts code for differential pair circuits using boundary scan receiver pins of type “inout”;
Adds capability to insert multiple lines in MESSAGE_PAUSE instructions. Lines are separated by newline characters,’\n’.
Reports line numbers for SIR instructions in scandata log files.
(Not Full Suite Validated)
Build 4638Adjusts ProScan to allow pin wiggling using older SVF files.
Adds additional filters to DTS syntax checking.
Corrects problem in ProScan where only nets with guards appeared Nets & Pins list.
Corrects problem with Trace:ShowPinConnects feature in ProScan.
(Not Full Test Suite Validated)
Build 4636Provides for use of SENSE guards in GuardsScanOnly files.
Improves fault coverage for JTAG devices having many shared control cells.
Makes syntax checking case sensitive for DTS script variables.
(Not Full Test Suite Validated)
Build 4634Corrects potential program exception when switching between ProScan and Development screens.
Build 4633Netlist composer now uses BSDL port names for the basis of assigned net names in XNF netlist file.
(Not Full Test Suite Validated)
Build 4632Updates ProScan:
- shows pin failures when single-stepping.
- ensures guards are incorporated when ‘wiggling’ pins.
- avoids reasserting Test Logic Reset on JTAG chains when TLR has been previously asserted.
(Not Full Test Suite Validated)
Build 4631Installer Update
Corrected DTS syntax checker for inserted SIR/SDR SVF strings
(Not Full Test Suite Validated)
Build 4628Corrects problem retaining settings in TestPlan.
Corrects potential program exception problem in ProScan when recompiling and reorganizing net positions.
(Not Full Suite Validated)
Build 4627Adds formatting options that add cancel buttons to the Ok and Yes/No MESSAGE_PAUSE dialogue.
Adds DLLs for Windows XP into new onTAP Install program.
(Not Full Test Suite Validated)
Build 4626Corrects potential crash condition in ProScan.
(Not Full Suite Validated)
Build 4624Introduces new Install program. Before installing, it is recommended that versions of onTAP previous to build 4324 be uninstalled using the Windows Control panel.
Edits the BREAKOUT cell and pin parsing format.
(Not Full Test Suite Validated)
Build 4623Introduces new Install program. Before installing, it is recommended that versions of onTAP previous to build 4623 be uninstalled using the Windows Control panel’s Programs and Features.
Tabular formats the BREAKOUT! cell and pin parsing report so that the text is readable in a text editor. BREAKOUT! Is accessible from the Debug menu.
(Not Full Test Suite Validated)
Build 4622Ensures that SAMPLE and Pin-wiggle functions work in ProScan when the Development screen is closed.
Upgrades the BREAKOUT feature accessible from the Debug menu. BREAKOUT parses SVF and scandata files to show TAP and measure values at each pin and cell at each scan vector.
Provides for the number of days that technical support is out of date to be returned when checking license in onTAP DLL.
(Not Full Test Suite Validated)
Build 4620Ensures that SENSE_HIGH and SENSE_LOW guards are asserted when TestGen’s Safe Mode is selected.
Corrects program exception conditions related to switching between ProScan, appXam, Development and Test views.
Revises appXam to faciltiate creating and updating basic application mode based tests.
Corrects syntax problem related to Compose Netlists using BSDL files.
Fixes incorrect failure post in Mid-state (resistive) Shorts procedure.
(Not Full Test Suite Validated)
Build 4619Corrects syntax checking of string variables.
Upgrades TestGen to handle mix of differential and non-differential boundary scan pins on the same nets.
Improves Find tool in ProScan’s Nets & Pins list.
(Not Full Test Suite Validated)
Build 4617Ensures reinitialization of settings on Cluster page when closing a cluster test project and then opening an interconnect test project.
(Not Full Test Suite Validated)
Build 4615Reorganizes installment package for Microsoft WinQual certification
(Not Full Test Suite Validated)
Build 4613Adjusts test generation for differential pairs when P side receivers are connected directly to N side transmitters.
(Not Full Test Suite Validated)
Build 4612Adjusts test generation for differential pairs so that OBSERVE_ONLY cells on differential transmitter pins are included in the test solution.
(Not Full Test Suite Validated)
Build 4610Provides additional correction for test generation on differential nets
(Full Suite Validated)
Build 4609

Corrects problem driving differential nets where each net has multiple drivers, some with shared tri-state control cells.

Corrects problem with TestGen page’s ‘Restore Default Settings’ where a BYPASS instruction was indicated in place of an IDCODE test instruction
(Not Full Test Suite Validated)

Build 4608Corrects potential program exception during test generation of cluster tests related to the addition of parallel test options in DTS models.
(Not Full Test Suite Validated)
Build 4607Corrects problem in test generation for parallel cluster test target devices.
(Not Full Test Suite Validated)
Build 4606Upgrades ‘Settings Change History’ in ProScan so that Attributes changed in the ‘Guards + Attributes’ tab appear in Settings Change History
(Not Full Suite Validated)
Build 4605Corrects test generation of circuits having differential pair pins with shared control cells and also connected to non-differential scan pins also sharing control cells.
(Not Full Test Suite Validated)
Build 4604Corrects handling of Network License Message problem related the Cluster Test option
(Not Full Suite Tested)
Build 4602Corrects message handling for string values set in ScanIR and ScanDR instructions.
(Not Full Suite Tested)
Build 4601Allows for instances of period characters in SVF file’s path name
Build 4600Upgrades .AUG style netlist translator.
(Not Full Test Suite Validated)
Build 4599Restores parallel test for cluster test applications allowing multiple target devices to be tested together.
(Not Full Suite Validated)
Build 4598Adds a dialog box when selecting Auto Detect on the Test screen to facilitate the auto detection of JTAG chains. The dialog box allows easy browsing and selection of a folder where BSDL files are located and also allows the A or B channel of an onTAP cable to be used.
(Not Full Test Suite Validated)
Build 4597Corrects problem involving test selection on the Test screen. The control and shift keys can be used to select multiple SVF files and the Check and Uncheck buttons on the Test screen can be used to ease enabling and disabling of tests for SVF files.
(Not Full Test Suite Validated)
Build 4596Restores correct operation to TRACE command in ProScan, showing all pin connections to selected pins.
(Not Full Test Suite Validated)
Build 4595Ensures that GUARD_STRING bits with a value of ‘X ‘ have the corresponding MASK bits set to ‘0’.
Corrects ProScan procedure that brings related pins in a test solution into proximity and tints them to highlight their relationship. The procedure is initiated by clicking on test vector values of a particular pin. The fix excludes power and ground pins from the test solution.
(Not Full Test Suite Validated)
Build 4594Sets TDI bits of negative side differential drivers. These TDI bit values should not be a factor for the corresponding observe_only cells but are now set on the chance that the cell is actually driving the N side of a differential pair.
(Not Full Test Suite Validated)
Build 4593Improves Test screen’s memory management.
(Not Full Test Suite Validated)
Build 4592Ensures repainting of the ProScan screen after recompiling an SVF file.
(Not Full Test Suite Validated)
Build 4591Allows recompiling after changing attribute values in ProScan without the need to close and reopen a project.
Corrects problem incorporating changes in jumpers list into application.
(Not Full Test Suite Validated)
Build 4590Automatically updates TestPlan on TestGen page to reflect any JTAG chain definition changes.
Sets license number to JTAG cable number or dongle number for embedded licenses.
(Full Test Suite Validated)
Build 4589Ensures that a a drive low vector occurs as the first vector in the opens faults test.
(Not Full Test Suite Validated)
Build 4588Corrects handling of how asynchronous key characters are loaded into the built-in ONTAP_KEY_CHAR variable in DTS models
(Not Full Test Suite Validated)
Build 4587Ensures that tri-state output pins having shared control cells and that have not been assigned a drive value do not change the value of a shared tri-state control cell.
(Not Full Test Suite Validated)
Build 4586Corrects problem showing incorrect test screen graphics.
(Not Full Test Suite Validated)
Build 4585Corrects occasional crash when changing views from Development screen to test screen.
Corrects test graphic for mid_state shorts tests.
(Not Full Test Suite Validated)
Build 4584Ensures that PRELOAD instructions, if they exist in BSDL file, are executed prior to CLAMP instructions.
(Not Full Test Suite Validated)
Build 4583Ensures that differential N side drivers designated as ‘out’ pins and ‘observe_only’ cells are not in test vectors.
(Not Full Test Suite Validated)
Build 4582Ensures that N and P side differential receivers are in opposite states.
Corrects test message that incorrectly shows ‘Testing…’ in some instances after a test completes.
(Not Full Test Suite Validated)
Build 4581Improves exit procedure on Test screen when processing failures for lengthy tests.
Allows cluster tests to be directly recompiled after editing circuit attributes in ProScan.
(Not Full Test Suite Validated)
Build 4580Adjusts procedure to create a .req file for remotely embedding licenses in onTAP JTAG controllers. To create an REQ file in C:\Flynn Systems Corp\onTAP folder, from License menu, switch to Embedded in JTAG Cable.
(Not Full Test Suite Validated)
Build 4578Corrects problem introduced in build 4577 when reopening onTAP Development software with embedded JTAG licenses.
(Not Full Test Suite Validated)
Build 4577Corrects program exception in TestGen related to IEEE 1149.6 AC differential test applications.
(Not Full Test Suite Validated)
Build 4576Safely restores onTAP DLL USB cable operation following a crash of a test executive running the onTAP C# DLL that is also using an embedded JTAG license.
(Not Full Test Suite Validated)
Build 4575Runs test generation faster for applications with many pins tied to ground net.
Improves capability to stop run-time tests during long diagnostic analysis procedures.
Corrects test generation problem for circuits involving pull resistors on the inputs of OR gates as well as other gates.
(Not Full Test Suite Validated)
Build 4574Corrects problem setting IDCODE instruction on the TestGen pages’s TestPlan
(Not Full Test Suite Validated)
Build 4573Adds text search in ProScan panels using direct keyboard entry.
(Not Full Test Suite Validated)
Build 4572Adjusts handling of N side differential pins in test generation when the N side transmitter is shown as OBSERVE_ONLY in the boundary register list.
Upgrades handling of jumpers settings files. Automatically converts pin-to-pin jumper expressions to net-to-net syntax. Original jumpers files are saved and backed up.
(Not Full Test Suite Validated)
Build 4571Improves project folder browse control on Project page.
(Not Full Test Suite Validated)
Build 4570Updates IEEE 1149.6 AC testing to allow for N side differential transmit pins that are designated as type “in”.
Runs TAP test and shows IDCODES for SVF files, as well as available test setup messages, when an SVF file is selected from SVF list on Test screen.
(Not Full Test Suite Validated)
Build 4569Corrects potential program hang condition on Scan page.
Simplifies procedure to use TRST(INIT cable wire) for GPIO purposes
(Not Full Test Suite Validated)
Build 4568Provides option to disable MID-STATE (resistive) shorts testing.
(Not Full Test Suite Validated)
Build 4567Adjusts diagnostic messages for pull-up and pull-down resistor tests when resistor connections are to header pins.
(Not Full Test Suite Validated)
Build 4566Adds option on TestGen page to base run-time diagnostic messages on header pins in place of related scan I/O pins.
Makes embedded JTAG cable license the default license condition when a license has not previously been selected.
(Not Full Test Suite Validated)
Build 4565Improves precision of diagnostic messages in resistor networks
(Not Full Test Suite Validated)
Build 4564

Tri-states TAP drive pins between scans for multiple JTAG chain applications, allowing TAP configurations where TMS, TDI and TDO pins in different chains can be connected in common.

(Not Full Test Suite Validated)

Build 4563Adds DIODE model to LogicPinMaps file and adjusts ATG to handle diode-resistor networks.
On Cluster page, shows instances where boundary scan pins do not have associated boundary scan cells.
On TestGen page, provides option to not include BSDL file recap in SVF file.
(Not Full Test Suite Validated)
Build 4562

Corrects tests report so that it flags test failures and indicates incorrect test values using U and D characters.

(Not Full Test Suite Validated)

Build 4561

Updates GPIO capability using TAP pins in onTAP’s JTAG Controller pod

(Not Full Test Suite Validated)

Build 4560

Adds capability on Cluster page to assign EXTERNAL pins to non-JTAG parts instead of directly to scan pins. onTAP in turn matches the non-scan pins to associated scan pins.

(Not Full Test Suite Validated)

Build 4559Corrects problem remotely updating embedded cable licenses.
(Not Full Test Suite Validated)
Build 4558Corrects potential program exception condition when switching from Developoment to Test screen.
(Not Full Test Suite Validated)
Build 4557Adds GPIO capability for USB Cable TAP pins that are not in use for boundary scan purposes.
(Not Full Test Suite Validated)
Build 4556Improves test generation for A/C IEEE 1149.6 differential pair tests between different JTAG chains.
Corrects Files 32 notice that pops up during onTAP installation.
(Not Full Test Suite Validated)
Build 4554Allows appXam pin lists to be populated on the basis of SAMPLE whatever application signals activity can be captured.
(Not Full Test Suite Validated)
Build 4553Corrects Auto Detect problems.
(Not Full Test Suite Validated)
Build 4552Adjusted TAP integrity tests that are initiated when clicking on Toolbar Test icon so that the tests are the same as when loading a test program.
(Full Test Suite Validated)
Build 4551Adds capability to test just TAP infrastructure of selected SVF files by clicking on the Test tab after a project folder has been opened on the Test screen.
(Not Full Test Suite Validated)
Build 4550Adjusts run-time code to ensure that TAP connect pods are interchangeable in applications using only one pod. Otherwise, adaptor files need to be reset to match pod channel assignments to specific JTAG chains.
For files copied to the Test Reports folder, the order of optional filename fields has been changed to ___filename.
Corrects problem using Auto Detect from Scan page.
Updates DLLs
(Not Full Test Suite Validated)
Build 4549Adds a Test screen option setting to append a time stamp to .test and .fail file names.
Adds a Test screen option setting to copy test files to a Test Reports sub-directory in a project folder.
Deletes link from Home screen to the Manufacturing Test screen, which has been consolidated to the Test screen.
De-emphasizes toolbar’s Development button for MTO licenses.
(Not Full Test Suite Validated)
Build 4547Corrects test generation problem when a shared control cell is assigned to an input pin which is connected to a ground or power net.
(Not Full Test Suite Validated)
Build 4546Adjust test generation when IEEE 1149.6 AC testing is enabled for capacitively coupled differential pairs when driver side is in a different JTAG chain than receive side.
Corrects potential crash condition when switching between test projects.
(Not Full Test Suite Validated)
Build 4544Removed the Nets and Manuf toolbar buttons. The Test screen should be used in place of the Manufacturing screen and ProScan should be used in place of Nets.
(Not Full Test Suite Validated)
Build 4543Updates response messages for license restrictions when using onTAP Network License Manager.
(Not Full Test Suite Validated)
Build 4542Improves JTAG chain assignments on Scan page. Adds spin control and edit box to adjust JTAG chain designations.
Corrects potential program crash condition during test generation.
Corrects flashing tab icon on Testability page.
(Not Full Test Suite Validated)
Build 4541Updates the Compose Netlist tool to facilitate creating a netlist derived from BSDL files and then beginning a Test Development project.
Adds TRACE circuit tool to list of ProScan instructions. TRACE detects and shows pin-to-pin circuit connections, useful in showing shorts faults as well as in rebuilding netlists that have been composed with BSDL files only.
(Not Full Test Suite Validated)
Adjusts for I/O INIT errors in onTAP TAP connect cable.
Build 4540Adds built-in function ‘ConvertBinaryStringToInteger’ for DTS model scripting.
Corrects error in extracting TDO data into ScanDR strings.
(Not Full Test Suite Validated)
Build 4539Corrects syntax checking problems for DTS cluster test models.
(Not Full Test Suite Validated)
Build 4538Restricts use of FAIL flag with pin groups assigned to variables in OG() instructions. When the results of an OG() instruction are to be tested with a FAIL flag, only single OG() instructions may be present on a DTS line.
(Not Full Test Suite Validated)
Build 4537Re-implements the appXam tool as a floating dialog and facilitates rendering application mode signals into useable tests. appXam is accessible from the ProScan main menu as well as from the Commands list within ProScan.
Improves syntax checking for semicolon characters in DTS models.
Updates to C++ and C# DLL avaialble
(Not Full Test Suite Validated)
Build 4536Enables FAIL flag when testing values of pin group variables in cluster tests.
Improves syntax checking for multiple declarations of variables in cluster test models.
(Not Full Test Suite Validated)
Build 4535Improves compiling and executing appXam test files.
(Not Full Test Suite Validated)
Build 4534Allows changing onTAP JTAG pods without updating adpator files in applications where only JTAG chains A & B are used in any of a project folder’s tests.
(Not Full Test Suite Validated)
Build 4533Improves ProScan's break-point and single-step operation.
(Not Full Test Suite Validated)
Build 4532Adds protection to safeguard interconnect and cluster test settings and to facilitate restoring and recovering settings.
Reports serial number of USB dongles on Licensing screen when entering screen and when changing dongles.
(Not Full Test Suite Validated)
Build 4531Adjusts licensing code for embedded USB JTAG cable licenses so that need to unplug/replug cable is reduced.
Updated onTAP C## DLL https://flynnsystems.com/files/downloads/onTAP_DLL_Csharp.zip
Updated onTAP C++ DLL https://flynnsystems.com/files/downloads/ontap_dll_demo.zip
(Not Full Test Suite Validated)
Build 4530Adjusts Mid State (resistive) shorts algorithm.
(Not Full Test Suite Validated)
Build 4529Corrects problem detecting Mid State (resistive) shorts in multi-chain applications.
(Not Full Test Suite Validated)
Build 4528Improves shorts detection of Mid State (resistive) shorts algorithm.
(Not Full Test Suite Validated)
Build 4526Added new edit box entries on the Test screen to facilitate use of Test screen in manufacturing environments. Entries include board serial number, operator and unit type.
Corrected inconsistencies when switching to Test screen from other screens.
(Not Full Test Suite Validated)
Build 4525Corrects pull resistor test problem introduced in build 4518
Corrects pull resistor test problem when multiple resistors including those designated ‘do not install’ are present on a net.
(Not Full Test Suite Validated)Corrects problem in ProScan when setting guards to disable failing tests on a net.
Build 4524Updates adaptor channel assignments of SVF files when clicking on Test Status column header.
Updates adaptor file to SVF assignments for multiple UUT and Parallel test environments.
(Not Full Suite Validated)
Build 4523Adds menu item on Test screen to move an SVF file to the top of the SVF file list. Right click on an SVF to access the popup menu.
Reduces load time when initially accessing a project folder.
(Not Full Suite Validated)
Build 4522Corrects adaptor file to SVF assignment problems.
(Not Full Suite Validated)
Build 4521Requires that all tests have adaptor files that match SVF file names to specific channel and serial numbers of onTAP USB JTAG adaptor cables. This protects against false pass conditions in applications having multiple UUTs.
Reduces programming time for FPGA and CPLD devices using SVF files.
Corrects crash condition when assigning scan pins on the cluster page.
Build 4520Reenables and upgrades operation from batch command files.
Build 4519Corrects diagnostic messaging in ProScan
Build 4518Corrects test generation problem related to logic gates driven by outputs sharing tri-state control cells.
Updates burn-in status messages.
Build 4517Corrects test generation problem related to differential pairs in IEEE 1149.6 AC.
Updates burn-in message problems.
Build 4516Corrects pass/fail messages for burn-in and looping tests.
Build 4514Integrates true parallel test capability for multiple boards into the Test screen.
Adjusts editing procedure for onTAP’s appXam tool. Cell selection is now done using right mouse clicks.
Build 4510Corrects problem reporting Burn-in test status on the Test screen.
Adjusts operation of View Fails and Reports buttons on Test screen so that selected tests in the SVF list file are viewed.
Build 4509Adjusts onTAP test expect capture values when HIGHZ and CLAMP instructions are assigned.
Build 4508Modifies Test screen so that most recent project folder is automatically selected.
Build 4506Adds test settings control to optionally omit .TEST report file and .FAIL diagnostic report when a test passes. See Test menu\Test and Burn-In Settings.
Adjusts automatic test model generation in appXam.
(Not Full Test Suite Validated)
Build 4503Adds check boxes to the SVF file list on the Test screen for purpose of selecting tests.Selected tests will be saved and restored when closing and opening onTAP. The opening comments on the Test screen’s context Help should be reviewed to note changes from previous procedures.
Upgrades the Licensing screen so that onTAP does not need to be closed and reopened after selecting a type of license.
Adds a GetStringLength() instruction for DTS models.
Build 4500Freshens style of onTAP screens and menus. Although functionality remains the same, the layout of controls on Toolbar, Menubar, Test screen and Projects page has changed.
Adds view of project folders on Test screen allowing easier access to tests within multiple project folders.
Build 4498Adds development tools to automate duplication of tests for multiple UUT applications.
Shows TAP Connect serial number assignments when loading tests on the Test screen.
Revamps Projects and TestGen pages and adds splitter controls.
Corrects parsing problem with space characters in MESSAGE instructions.
(Not Full Test Suite Validated)
Build 4497Corrects problem when using the No Test setting on the Non-Scan page.
Corrects syntax error warning when ‘ERASE” is used in a MESSAGE instruction.
(Not Full Test Suite Validated)
Build 4496Extends fault coverage reports to include a sort by JTAG devices. A LogicReports file is placed in a project folder’s reports sub-directory when ‘Sum Checked’ is selected from the Reports tool, accessed from the Reports menu item.
(Not Full Test Suite Validated)
Build 4495Adds corrections for DTS MESSAGE instructions.
(Not Full Test Suite Validated)
Build 4494Corrects syntax error related to using pin names as arguments in MESSAGE strings.
(Not Full Test Suite Validated)
Build 4493Upgrades performance for burn-in operation.
(Not Full Test Suite Validated)
Build 4492Additional corrections and added syntax checking for ScanIR/ScanDR and MESSAGE instructions.
(Not Full Test Suite Validated)
Build 4489Corrects Save/Restore problem when inserting instructions into the TestGen page’s TestPlan
(Not Full Test Suite Validated)
Build 4488Adds error check for ScanIR/ScanDR instructions during test generation.
Corrects string handling in MESSAGE_FILE instructions.
(Not Full Test Suite Validated)
Build 4487Corrects problem loading Xilinx SVF configuration programming files.
(Not Full Test Suite Validated)
Build 4486Reduces TestGen compile times
(Not Full Test Suite Validated)
Build 4485Enables multi-chain capability for ScanIR and ScanDR instructions controlled by the TAPMAP instruction.
Corrects problem handling local string variables.
(Not Full Test Suite Validated)
Build 4483Includes additional updates and fixes for the ScanIR and ScanDR instructions.
Includes adjustments for screen flicker.
(Not Full Test Suite Validated)
Build 4482Includes updates and fixes for the ScanIR and ScanDR instructions.
(Not Full Test Suite Validated)
Build 4481Adds TestGen interconnect option to set default value of don’t care TDI bits to ‘0’ or ‘1’.
(Not Full Test Suite Validated)
Build 4480Includes updates and fixes for the ScanIR and ScanDR instructions.
(Not Full Test Suite Validated)
Build 4478Includes updates and fixes for the ScanIR and ScanDR instructions.
Adds built-in variables TDO_HEX_DATA and TDO_BINARY_DATA which capture TDO scan data when LogScanDataOn() is active.
(Not Full Test Suite Validated)
Build 4477Reduces screen flicker.
Build 4476Adds ScanIR and ScanDR instructions to DTS models. ScanIR allows IR scans to be loaded from within a DTS model on the basis of TAP opcode instructions assigned to each device in a JTAG chain. ScanDR provides capability to compose data register values on the basis of string variables.
Writes ShowPass(message) and ShowFail(message) messages to the .test report file.
Adds built-in strings MTO_SN,MTO_OPERATOR, and MTO_UNIT_TYPE that capture related inputs on the MTO screen and can be used in MESSAGE instructions. Also SVF_TESTNAME contains the name of the current test.
(Not Full Test Suite Validated)
Build 4475Adds correction for using hexadecimal notation in user script files.
Addresses issue of incorrect scroll bar operation on Test screen.
(Not Full Test Suite Validated)
Build 4474Adds appXam feature which creates boundary scan tests and diagnostics based on qualified application mode signals. See Help on ProScan page for details.
Adds Deploy menu item allowing users to control populating the ‘test_files_for_deployment’ folder.
Adds capability to move selected pins and nets to the top of the ProScan view.
Adds capability to quickly remove guard conflicts that are reported on the Cluster page.
Ensures that deselected bypass tests in multiple chain applications are in fact not included in TAP tests.
Updates adaptor file settings in TestGen’s TestPlan so that when settings are changed for a JTAG chain in one instance then settings are updated for all instances.
Corrects problem with save-restore no-test setting on the Non-Scan page.
Automatically updates Test screen test when switching focus from Development and ProScan pages.
Allows inserting SIR, SDR, and SVF instructions directly into DTS models so that the resulting scans are included in compiled SVF folders.
(Not Full Test Suite Validated)
Build 4473Corrects problem in adding test files to the ‘test_files_for_deployment’ folder.
(Not Full Test Suite Validated)
Build 4472Adds handling of hexadecimal notation in user-defined test scripts. See User Defined Tests in onTAP Help.
(Not Full Test Suite Validated)
Build 4469Corrects resizing issue in ProScan’s Circuit Browse tab.
Corrects program exception problem in ProScan when alternating between application sampling and pin wiggling operations.
Build 4468Adjusts newline formatting in MESSAGE_FILE instruction so that if newline, \n, escape sequences are inserted in text then onTAP will not insert an additional newline at the end of the text
Build 4467Adjusts window synchronization in ProScan’s splitter views.
Adds newline formatting to DTS MESSAGE_FILE instruction.
Restores correct operation of the ShowMe! debug tool.
Build 4465Improves consistency of TestabilitySurvey reports when summing reports using the Reports tool.
Build 4464Improves consistency of TestabilitySurvey reports when summing reports using the Reports tool.
Corrects syntax error reporting for DTS models when parentheses characters are used in string variables.
Build 4463Adds formatting capability to DTS MESSAGE instructions so that messages can be directed to specific Message window lines using a \L directive. In addition a ClearMessages instruction has been added to clear the Message window. See MESSAGE in online Help and the ‘led_test_with_asynch_key_input.dts’ model in onTAP’s ‘DTS Models\LEDs” folder.
Build 4462Restores onTAP UI to build 4457 style and look.
Build 4461Corrects missing menu problem running on Windows XP.
Build 4460Adds asynchronous key input control capability to DTS models allowing a loop in DTS to run while monitoring keyboard input. See See ONTAP_KEY_CHAR in Help.
Adjusts screen sizing controls.
Build 4459Corrects handling some math expressions in DTS instructions.
Corrects BSDL syntax warnings related to differential port groupings.
Adjusts screen styling and adds to menu bar items.
Build 4458Adds error status codes for onTAP USB cable.
Adds dynamic TRST for Auto Detect JTAG Chain function.
Build 4457Improves handling of situations when Windows does not have a device handle available for the onTAP USB cable, automatically cycling a disconnect/reconnect sequence.
Build 4456Strengthens ProScan code to protect against program exceptions
Build 4455Adds HexToString instruction for DTS models.
Build 4453Adds StringToHex instruction for DTS models.
Build 4452Adds capability to assign return value from the SystemCall function to an integer variable.
Build 4451Corrects Development screen problems with 1600x900 resolution setting.
Build 4450Upgrades GenRad In-Circuit Test ATE translator.
Corrects problem with DTS instruction of form MESSAGE_FILE(%s,ERASE,filename)
Build 4449Adds correction for automatic netlist insertion when using the MultiChipModule file.
Restores HTML Home page.
Adds custom USB adaptor file setting for ESCAPE COMM.
Upgrades more Help pages.
Adds S70GL flash model.
Introduces waveform display for test signal values in ProScan.
Shows Application signal sampling (Application SAMPLE command) in the waveform display.
Build 4448Replaces Home screen and corrects program loading problems related to home screen
Provides support for customer FTDI USB-JTAG devices that use opposite output enable polarity than does onTAP.
In ProScan, shows Application SAMPLE values in the vector display as well as in the Browse Circuit display, so that application sampling values can be more easily scanned and viewed.
Adds waveform view to ProScan, which can be toggled to show test vector values either as waveforms or as 01LH values. A toggle for this purpose is in the conmmand list.
Build 4445Adds string handling instruction GetProjectFolderName() in DTS Models to get the active project folder name.
Adds capability to concatenate string values using ‘+’ as in string1 = string2 + “some text” + string2 + “more text”;
Adds capability to use string variables or string text as arguments in the SystemCall() instruction. For example: SystemCall(copy,”myfile.txt”,your_folder_name_string_var);
Build 4444Corrects problems with Test USB Cable Pins procedure, located on Cables menu page, for onTAP TAP Connect probe
Build 4442Eliminates incorrect erasing of diagnostic pin_fails files.
Build 4441Adjusted use of %L device identifier in DTS messages so that it is independent of other message delimiters.
Adjusted layout on Jumpers page.
Build 4440Adds capability to pass strings to subroutines
Adds capability to pass integer and string variables by reference to subroutines
Modifies screen configurations so that full-frame is the default for each view.
Build 4438Updates and adjusts flash programming messages.
Build 4437Upgrades onTAP’s backup and restore functions.
Build 4436Update onTAP DLL to allow for repeat license enable requests.
Corrects test generation for some logic gate configurations
Build 4435Corrects problem saving DiffPairsList files.
Updates synchronization and settings for guards and attributes between windows within ProScan.
Build 4434Further adjustments for the DLL’s GetIdcode instructions.
Build 4432Adjusts GetIdcode function in onTAP DLL so that it will work when an IDCODE is obtained after a cluster test is run.
Build 4431Corrects problem with GetIdcode function in onTAP DLL and updates DLL on download site.
Build 4430Adjusts licensing to avoid pop-up messages for new installations using embedded licenses in JTAG cables or dongles.
Selects embedded JTAG cable license from a mix of JTAG cables with and without licenses.
Allows screens to be adjusted to full-frame presentation.
Adjusts the default test values for IEEE 1149.6 AC hysteresis FFs so that the opposite of expected test values are captured when the circuit between differential drivers and receivers is open.
Build 4428Ensures assignment of selected boundary scan pins to target cluster test pins when a choice of BS pins is available.
Eliminates command prompt message “Number of devices” when the onTAP DLL is run from a command prompt.
Updated onTAP DLL download files.
Build 4427Corrects problem related to the application of guard assignments.
Build 4426Adds support for PCad netlist format.
Build 4425Added window splitters to Circuit Browse screen in ProScan.
Build 4424Corrects program exception in onTAP DLL when using uppercase string delimiter %S in MESSAGE_FILE instructions.
Corrects syntax handling problem when assigning text within quotation characters to string variables.
Corrects problem calling one sub-routine from another sub-routine when local variables are used.
Updates onTAP C++ and C# DLLs.
Build 4423Adds support for BSDL KEEPER function which is implemented in the pull resistor tests by setting the expect capture value to the value of the last drive value on the net.
Build 4422Facilitates restating onTAP USB cable after placing PC in overnight ‘sleep’ mode.
Adjusts ProScan summary test message.
Build 4421Provides selectable state resets for each JTAG chain.
Build 4420Adds capability to mix GPIO and EXTEST boundary register scans in the same DTS model.
Corrects crash condition related to certain multiple chain configurations during test generation.
Build 4419Protects against inadvertent changes to TestPlans, for example after redefining JTAG chains. Added capability for editing on the TestGen page allows users to directly modify test plans. The ‘Delete Test Plan Item’ insyruction can be used to delete devices in JTAG chain and the chain entries can be edited.
Build 4417Adjusts procedure to remotely update embedded licenses in onTAP USB JTAG cables.
Build 4415Corrects problem on Cluster page where the text “check” is incorrectly placed in the DTS Header plug-ins list.
Corrects inconsistencies when using pin-wiggler function.
Build 4414Upgrades tool to extract populated and non-populated devices from a BOM spreadsheet.
Build 4413Fixes use of variable file name in MESSAGE_FILE/ERASE instruction
Build 4412Updates handling of SVF configuration programming files.
Build 4411Restores Pin Wiggle functions in ProScan for conditions where a test application is not loaded on the Development screen.
Ensures that nets are only listed once in the TestabilitySurvey report.
Build 4409

Fixes and modifies the fault insertion procedure. See ‘FaultInsert’ in Help. SVF files compiled before build 4409 must be recompiled in order to use the upgraded FaultInsert.

Upgrades diagnostic messages for opens faults.

Build 4408Corrects incremental horizontal scrolling in ProScan.
Build 4406Upgrades GetSubString function.
Build 4405Adds capability to capture TDO data when using SDR insert instructions on the TestGen page. TDO data is captured into an built-in string variable named TDO_CAPTURE.
Adds GetSubString instruction for DTS models. example: my_string = GetSubString(input_string, index,delimiter_string); where my_string and input_string are string variables, index is a value or integer variable, and the last argument is a string of character delimiters which separate the strings.
Build 4404Improves test generation and fault coverage through non-JTAG circuits
Build 4403Adds capability to directly assign integer variables to string variables as well as string variables to integer variables.
Displays IDCODES messages in hexadecimal format as well as binary format.
Upgrades onTAP DLL so that the fail record file shows detailed IDCODE values and failures.
Adds GetHexIdcodes() function to the onTAP DLL.
Reverses string value in GetIdcode DLL function..
Build 4402Adds capability to insert a pattern on the onTAP JTAG cable INIT pin. INIT Pin instruction can be dragged onto the TestPlan.
Build 4401Improves test generation for larger multi-chain applications.
Build 4396Corrects test generation solutions for some large circuit applications.
Adjusts opens faults diagnostic messages when opens occur on different nets across non-scan devices.
Build 4395Provides added lower/upper case control for hexadecimal strings in cluster test messages. Use %x syntax to output lower case hex and %X syntax to output upper case hex.
Build 4393Corrects problem with assigned ‘expect’ values for some test generation solutions.
Extends size of edit box in ProScan’s ‘find’ tool.
Build 4392Adjusts line scrolling on ProScan screen.
Build 4391Speeds up loading applications and scrolling scan vectors in ProScan.
Build 4390Upgrades test generation output when managing multiple outputs on a net.
Corrects problem in ProScan when reordering related test pins and vectors.
Adds right-click menu item in ProScan to suspend feature that reorders related pins and test vectors.
Build 4388Upgrades and corrects ProScan functions ‘Find First Fail’, ‘Find Next Fail’, and ‘Find’.
Upgrades capability to click on a pin fail message and locate the pin in the Nets & Pins list.
Build 4387Rebuilds the capability in ProScan to show nets and pins together that are related in a test solution. Left click or hover mouse over a scan vector character to bring related pins together, which will be shown with a tinted background
Build 4386Corrects problem using syntax, %L, to identify logic elements in MESSAGE instruction.
Corrects problem related to ERASE in MESSAGE_FILE instruction when the filename is in a variable..
Generalizes use of token names when inserting SDR instructions in TestGen.
Build 4385Corrects problems when inserting SDR,SIR,or MESSAGE instructions in a test plan on the TestGen page.
Build 4384Corrects crash condition in TestGen when compiling large multi-chain applications.
Build 4383If the PRELOAD instruction code differs from the SAMPLE instruction code, ensures that PRELOAD is used to load first vector when SAMPLE/PRELOAD is selected.
Adds separate SAMPLE/PRELOAD option for Cluster Tests.
Build 4382Corrects potential test execution problem when multiple pin groups are used in one DTS instruction.
Build 4381

Adds option to select ‘0’ or ‘1’ TDI don’t care bit values for cluster tests. See Cluster Test options on TestGen page. For existing test plans, click on Restore Default Test Plan first.

Ensures that MASK bits for SIR instructions are properly set during TAP related tests.

Build 4379Makes the default TDI drive value for all don’t-care output pins a logic one value. This generally affects cluster tests only.
Build 4378Corrects placement of Auto Detect BSDL files on Scan page.
Adds fault count to Guards+Attributes panel in ProScan. This helps avoid switching away from this panel during debug.
Ensures that the default drive value of uncontrolled buffer pins is a logic one value.
Build 4377

Adds capability to access the active test name in a DTS model so that data can be written to a file using the test name to form a file name. See GetActiveTestName in online Help – The DTS Program Format.

Changes useage of the %L modifier so that a pin group name argument is no longer required in a string with the %L syntax. Any pin declared in a DTS header may be accessed and expressed in the MESSAGE instructions using %L:dts_name. For example %L:DQ7 would be translated to U8.AB3 if DQ7 is assigned to pin AB3 on device U8.

Corrects problem assigning headers on Development screen’s Cluster page. Select .hdr file in DTS Header plug-ins list to replace the package pin assignments header section in a DTS model.
Adds instruction allowing text or string variables to be concatenated to a string in DTS models. Examples:
string st1,str2;
str1 = text1;
str2 = “text2 +”;
str2 += str1; // str2 => “text1+text2”

Updates onTAP DLL and adds several new DLL instructions:
SetLicenseType // allows user to specify license style, for example network license or license embedded in JTAG cable.
GetIdcodes // allows test executive to access IDCODES for specific reference designators after running an SVF file.
Callback function NotifyRunTimeMessages that sends messages that would appear in onTAP’s Test screen Message window to the DLL test executive program.

Updates DLL document and places a C# demo showing DLL instructions on Flynn Systems website.

Adds DTS instruction GetKeyDownCount which can be used to break out of a loop by noting the the value of GetKeyDownCount before entering the loop and then checking GetKeyDownCount while in the loop.

Build 4374Adds a capability to override and replace onTAP’s ATG test solutions with user-defined solutions. This added flexibility helps produce test solutions for some non-JTAG circuits where the user knows the test solution and onTAP has not created a correct or complete solution. See Test Solution Override item in the Tools menu.
Build 4373Corrects potential crash condition during test generation.
Build 4372Corrects possible cell assignment problem involving EXTERNAL pin designations in cluster tests.
Build 4371Introduces capability for test developer to override onTAP test generation solutions with developer’s own solutions. Search for ‘override’ on the TestGen page’s online help for implementation details.
Build 4370Corrects crash condition detected when writing some test reports during test generation.
Adds BSDL syntax check warning when pin is declared as ‘inout’ but appears in boundary register as an OUTPUT2 without a control cell.
Build 4369Corrects problem showing scan pin assignments for type ‘in’ pins on the Cluster page and ShowMe! page.
Prevents updates to onTAP USB cable adaptor files from TestGen page unless the adaptor settings have been altered there.
Build 4368Adds capability to insert a timestamp DTS message instructions. Reference TIMESTAMP in “The DTS Test Program Format” online Help.
Adds capability to insert newlines in DTS message instructions, using newline escape sequences, as in MESSAGE(“line1\n line2”);
Adds note to the online Help document ‘The DTS Test Programming Format ‘ to use parentheses in compound logic expressions such as ‘if ( (A == B) && (C == B))’
Build 4366Corrects screen update problem with Reload Guards button on Guards page.
Build 4365Corrects problem involving false failures in multiple JTAG chain applications.
Corrects potential omission of some TAP tests when updating older revision SVF files.
Corrects program crash when running using PlayRecordBinaryOn function and not using Flash Control panel.
Build 4364Corrects problem with order of SVF files when group-selecting SVF files whose names include spaces.
Build 4363Corrects problem when rewriting USB JTAG cable adaptor files from the TestGen page.
Adds preliminary EXTEST ‘write’ scan when the SAMPLE/PRELOAD is not selected on the TestGen page. Correction applies to the first instruction in Cluster tests.
Build 4362Adjusts ShowMe! column size to adapt to any size pin group.
Additional updates for screen resizing.
Build 4361Updates and adjusts screen sizing
Build 4360Updates logics and DTS models.
Restores operation of Guards page PIO control string for TRST (INIT) pin.
Build 4359Simplifies managing USB cable adaptor files: automatically connects B channel ports independently of onTAP USB cable serial numbers so that adaptor files for single JTAG chain applications do not need to be edited.
Automatically resets USB ports when starting onTAP.
Adjusts dimensions for user controls on onTAP screens.
Updates onTAP DLL.
Build 4358Corrects problem with pulldown and pullup tests.
Build 4357Includes guard settings in ProScan’s Pin Wiggler. Guards are asserted by default on guarded pins when pin wiggling. This can be overriden by changing guards(recompile is unnecessary) or wiggling a guarded pin itself.
Build 4356Improves access to onTAP USB Cable ports.
Update onTAP DLL.
Build 4355Improves screen rendering on the Test, TestGen and ProScan screens.
Build 4354Correct problem affecting operation of DDR3 memory test models.
Build 4353Ensures that all JTAG pins, assigned using an EXTERN declaration in cluster tests, are shown in the ProScan presentation.
Corrects Flash Control panel’s handling of erase instructions when using binary flash data files.
Build 4352Adds an estimated potential fault coverage score at the bottom of the TestabilitySurvey report. The estimate is based on available boundary scan pins as well as on DTS cluster model assignments and transparency model assignments made on the Non Scan page.
Build 4351Upgrades the TestGen page’s TestPlan operation so that if the TAP test is not checked, then individual parts of the TAP test will not be produced, even if they are checked.
Build 4350Adds TestNoConnectPins settings option to the TestGen page.
Build 4349Updates TestPlan when cluster tests use Copy Settings to initiate a new cluster test based on the settings of an existing cluster test.
Build 4347

Corrects potential problem with pullup-pulldown tests when a two state buffer pin is on a net.

In ProScan, corrects pin-wiggling after nets have been reordered.

Build 4346Updates BSDL OPCODE assignments on the TestGen page when user overrides default assignments.
Build 4344Incorporates improvements and changes to the flash programming PlayRecord operation.
Build 4343

Speeds up diagnostic analysis.

Refines and improves the DiagnoseHardFaultsOnly option. Adds capability to control enable of option using entries in the Test menu.

Shows guards for cluster test applications in ProScan.

Ensures that guards are held during flash device PlayRecord playback.

Corrects problem placing some JTAG devices in Bypass mode.

Build 4342

Separates pins having NC (no connect) net designation so that no-connect pins can be individually tested.

Adds a DiagnoseHardFaultsOnly option to the Interconnect Test Options list on the TestGen page. This option controls diagnostic test messages so that sporadic and intermittent failures are ignored and only faults having a hard fault (opens,stuck-at, and shorts) signature are diagnosed.

Build 4340Adds capability to use DTS instructions to control the GPIO pins on FTD12232D and FT2232H chips
Build 4339

Adjusts Allegro netlist translator to accommodate additional syntax and keywords.

Corrects potential stall when running a batch of SVF files.

Build 4337

Adds capability to match onTAP JTAG USB Cable channels to specific JTAG chains on the Development screen’s Scan page. This helps relate physical channel ports to JTAG chains early in the development process.

Faciliates changing test settings from a cluster test to an interconnect test.

Build 4336

Simplifies handling merged net names and component reference designators for assemblies having a prefix string assigned during the merge. Resistor components on such assemblies are automatically matched to an onTAP model.

Corrects creation of chain and port assignments in adaptor files when generated from the TestGen page. Applies to multi-chain/multi-usb-cable applications.

Enhances ProScan to show related pins of AC differential pairs together in netlist.

Build 4335

Adds capability to remove embedded jumpers in merged netlist files. The merged_netlists.src file is the source netlist after using the merge tool. If ‘Retranslate Netlist’ is selected on Projects page, the merged_netlists.src will be copied to the merged_netlists.xnf netlist.

Improves test generation for circuit configuartion of multiple resistors connected to a common tie point and then to scan pins.

Build 4334Corrects problem in previous build related to matching pin names in BSDL files with corresponding pin names in netlist files.
Build 4333

Updates netlist merge procedure. Copy the merged_netlists.src file to a project_folder and onTAP will make the necessary netlist filename adjustments.

Updates TestPlan to automatically include changes in JTAG chain definitions.

Adjusts BSDL BGA package pin names when leading ‘0’ characters are inserted at the beginning of a numeric sequence.

Build 4332

Fixes program exception problem when selecting pin name in Signals list.

Correct problem managing signal values during pull down resistor tests for nets connected to ground through low Ohm resistors.

Build 4331

Updates support for IEEE 1149.6 A/C testing where multiple serial capacitors lie between differential transmitter and receiver.

Updates GenRad ICT translator to run with settings on new TestGen screen.

Build 4330Updates Network License Manager options indicators in Licensing menu.
Build 4329

Adds several new features to ProScan: 1. Clicking on a pin in the Nets & Pins list will reorganize the list so that other nets and pins having related test solutions are inserted immediately below the clicked pin. Each pin related in a test solution will also be tinted. 2. Clicking on an H or L test value in the vector section will show related test steps and circuit elements in the message area.

Corrects a bug in TestGen when inserting an SIR instruction from the Available Instructions list.

Build 4328Cleans up some legacy code that unnecessarily repeated data scans.
Build 4327

For cluster tests, adds automatic handling of termination resistors between differential clocks so that user does not need to find them and set the high_impedance attribute.

For cluster tests, upgrades setting of EXTEST and BYPASS OPCODES taking into account active guards as well as scan pins required by DTS cluster test models.

Build 4326

Adds test generation correction for logic circuits.

Updates writing adaptor file for Xilinx Cable IV.

Build 4325

In User Defined scripts, ensures that scan data is correctly assigned to bit-string variables.

Updated parallel IO strings asserted from the guards page.

Build 4324Adjusts EDIF netlist translator.
Build 4323Upgrades JTAG Chain Auto Detect for applications with a mix of JTAG devices that have and don’t have IDCODE registers.
Build 4322

Corrects Cluster page problem after copying settings from an interconnect test to setup a cluster test.

Automatically detects embedded JTAG cable and dongle licenses.

Build 4321

Adds tools to the TestGen page so that scans and instructions can be inserted directly into a Test Plan.

Adds capability to embed portable licenses into the onTAP JTAG USB Cable or into the USB dongle.

Combines Settings page items into the new TestGen page.

Adds capability to setup JTAG adaptor cable from the TestGen page.

Fixes test report so that alternate IDCODES in the idcodes_allowed file are shown as passing.

A Users Name box has been added to the Projects page. Project history (MRU) lists are maintained on a user name basis.

Adds netlist translator support for Intel’s net_rep and net_cpn netlist text files.

Enhances test generation for applications having large numbers of common tri-state control cells.

Build 4320

Adds tools to the TestGen page so that scans and instructions can be inserted directly into a Test Plan.

Adds capability to embed portable licenses into the onTAP JTAG USB Cable or into the USB dongle.

Combines Settings page items into the new TestGen page.

Adds capability to setup JTAG adaptor cable from the TestGen page.

Fixes test report so that alternate IDCODES in the idcodes_allowed file are shown as passing.

A Users Name box has been added to the Projects page. Project history (MRU) lists are maintained on a user name basis.

Adds netlist translator support for Intel’s net_rep and net_cpn netlist text files.

Build 4318Adds built-in DATA_FILE string variable to DTS so that conditional statements can be used within DTS models. DATA_FILE is automatically assigned the file name argument in the OpenProgramFile instruction’s file argument.
Build 4317

Automatically retranslates a project netlist when using the Copy Settings tool on the Projects page.

Changes the source netlist for merges to merged_netlists.src so that merged_netlists can be refreshed when different jumper settings are used from test-to-test within a project.

Build 4316Corrects test generation problem involving multi-stage non-scan two-state logic. Scan pins are programmed to be tri-stated on nets driven by two-state non scan output pins.
Build 4314Corrects problem adding jumpers to no-connect pins.
Build 4311Upgrades handling of hex strings in user defined script files
Build 4309

Upgrades Alternate IDCODES, accesses from Tools menu, so the measured IDCODES can be accepted as alternates.

Upgrades ProScan so that the vector presentation of all pins in a test solution, independent of net assignments, are presented together, creating a clear view of relationships between drivers and receivers.

Build 4308

Adds a new Byte Unpack Order control on the Flash Settings control panel, providing a simple means at run-time of reordering the sequence in which bytes and words are read from a FLASH data file. See help on that screen to see how the unpacking order of bytes in a flash data file can more easily be specified.

Adds a drag and drop procedure to associate non-JTAG models to user’s circuit locations on the non-Scan page.

Build 4304

Adjusts Concise netlist translator so that only the first instance of a component location in the pin list needs to have a device type assigned.

Corrects problem using Retry On Failure setting when running from the ProScan screen.

Build 4301

Adds capability in DTS models to interact with test executives via the onTAP DLL. Instructions have been added to get and set integer and string values based on token values. See Set_DTS_integer,Set_DTS_String, Get_DTS_Integer,GetDTS_String in onTAP Help.

Improves instructions for USB adaptor cable self-test on Test screen’s Help.

Adds feature option on Development screen’s Project’s page to include a netlist insertion file in project. See Project page’s context help.

Build 4300

Added capability to view Flash verify results using access from Flash Settings Control Panel.

Added new capability to Flash Control Panel for start and end flash programming address settings.

Adjusted dimensions on Test screen

Build 4299

Corrects problem in MID-STATE shorts test where some resistive shorts faults were not detected.

Corrects problem with Wait Cursor not terminating on TestGen page.

Build 4296Adds capability for user to change I2C device address on Flash Settings control panel.
Build 4294

Upgrades FLASH Control Panel to include an optional number of TCK clocks between programming addresses, allowing more time for programming operations.

Upgrades IEEE 1149.6 AC testing so that jumpers are not required across capacitors. Capacitors in the test should be matched to onTAP’s CAPACITOR model on the Non Scan page. Loopback connections are best handled using a ProjectPinMap.txt model of a connectors pin-to-pin connections. The ProjectPinMaps file is located in a user’s project folder.

Build 4291Introduces a User’s Control Panel for run-time FLASH programming and verifying settings. The Control Panel is accessible from the Test screen and the Test menu.
Build 4290

Upgrades PlayRecord feature for flash programming.

Upgrades ability to assign net names to pin in Compose Netlist tool.

Upgrades handling of binary flash data files.

Upgrades DLLs.

Build 4289Speeds up scrolling and test program execution in ProScan.
Build 4288

Provides capability to access EXTENDED_ADDRESS, SEGMENT_ADDRESS and low word address, LOW_ADDRESS, from within DTS programming and verify models. Previously this information was available only within the FILE_ADDRESS variable.

Enhances capability using the Compose Netlist tool to build netlists based on BSDL files and the Auto JTAG Chain Detect tool.

Corrects DTS DISABLE section for GenRad ICT chain applications.

Makes adjustments for Chinese language screen presentations.

Build 4287

Corrects parsing restrictions when translating User Defined Script files with the Compose SVF file tool.

Ensures that INSTRUCTION CAPTURE tests are not implemented for any instruction loading scans if “tap instruction capture” is not selected on the TestGen page

Build 4285Cuts NAND FLASH programming time at least 3X!
Build 4283

Modifies and improves test generation related to assigned logic elements.

Includes Net Order list, used to show sequence of net names in ProScan, in Copy Settings operation.

Build 4281General update for improved test reporting.
Build 4279Upgrades and corrects cluster test operation in multiple JTAG chain environments.
Build 4278Upgrade for operation with onTAP Network License Manager.
Build 4276

Corrects problem presenting all diagnostic messages for TAP test failures.

Adjusts synchronization with onTAP Network License Manager server .

Build 4274

Speeds up reloading test projects on the Development screen.

Improves management of changes to the jumpers list.

Upgrades auto detection of JTAG chains. Results are placed in a file as well as shown on the Test screen

Build 4273Removes restriction against use of period characters in path name to project folders, although including period characters in path names is not recommended.
Build 4272

Adds capability to place related differential pair nets together in test report and on ProScan screen.

Upgrades ability to add alternate IDCODES. See Test menu.

Build 4271

Adds capability to diagnose only opens faults and filter out other faults for a/c coupled differential pins. See Diagnose Only Opens on Development screen’s Settings page.

Upgrades .test file, accessed using View Test Report button on Test screen. Test values are truncated at the point where a test file stops in the events that the fault count exceeds MAX FAILS. ProScan screens have been upgraded in a similar manner.

Build 4270Upgrades diagnostic processing
Build 4269

Adds search control on Non-Scan page to search for model names.

Adds capability to test only differential circuits while disabling other test activity.

Upgrades diagnostic resolution for circuits having intermittent test results.

Corrects potential program exception problem when jumpers are added.

Build 4266Adds a tool to the Cables menu that facilitates updating a project’s adaptor files when an onTAP USB Dual Port cable is replaced
Build 4265

Corrects problem displaying DTS lines in ShowMe! debug tool.

Corrects crash condition that could occur when maximizing and minimizing screens in a particular sequence.

Provides additional updates for TestGen page settings and procedures.

Corrects problem showing negative numbers in reports files for nets not having scan pins.

Build 4260

Corrects problem restoring HIGHZ test procedure name when reloading a test on the TestGen page.

Corrects problem running large test suites on the MFG Test screen.

Build 4259

Updates onTAP so that IEEE 1149.6 A/C tests work with multiple JTAG chains and onTAP USB cables.

Corrects problem restoring Clamp instruction when reloading a test on Development screen.

Upgrades user test messages on Test screen.

Corrects test generation handling cells where the control cell is the same as the drive cell.

Corrects problem in cluster tests when using OL and OH instructions on external pins that are not in a pin group.

Build 4257

Adjusts TCK rate adjustments in the Test and Programming Cable dialogue.

Adjusts for IEEE 1149.6 operations when testing across multiple JTAG chains

Build 4256

Improves test generation and management of bus signals when bidirectional pins share a common tri-state control cell.

Adds capability to set more guards using the Guards+Attributes tab within ProScan.

Shows all pins on Jumpers page. Previously, only devices having more than four pins were shown in the FromPin and ToPin lists.

Build 4253Shows header package pin assignments for Cluster tests on the Cluster page.
Build 4251

Adds additional Debug menu items including the ability to learn measured test results and to disable tests at individual test vectors during debug

Upgrades capability in ProScan to examine ATG results for individual pins and to produce individual test scans to check the ATG results. This is intended to help debug test activity in complex non-scan circuits.

Build 4250Adjusted some screen layouts including positions of controls.
Build 4249

Ensures that all pins are properly updated in cluster test applications having multiple chains where pin instructions related to more than one chain are used in the same scan.

Corrects Manufacturing screen layout problem with Cable Test group control box.

Upgrades GUARD STRING editor allowing guards to be set on a per vector basis as well as on a per pin basis.

Build 4248

Upgrades test reports, fault coverage reporting format, and tool to summarize fault coverage reports. See onTAP Reports menu.

Adds tool to automatically create a loopback list for connectors, helpful when logic devices separate connector pins from access to scan pins. See “loopback” in on line Help.

Adds DTS Library models and makes them accessible from Cluster page.

Adds flash programming models for S29AL032 as well as several logic models.

Improves fault coverage in environments with many logic devices, buffers, and transceivers between scan pins.

Corrects potential problem related to EXTERNAL pin declarations in DTS models.

Corrects problem reliably showing scan pin assignments and target device pin matchups on Cluster page.

Corrects problem with memory leak affecting some applications.

Updates DLLs.

Build 4247

Introduces a new capability to reduce flash programming times by recording programming overhead and flash data in a binary record file. See “PlayRecordBinary” in the DTS Test Program Format document within onTAP Help.

Reduces test execution time within the ProScan environment.

Adds capabillity on the TestGen Development page to more clearly change cluster test modes of JTAG devices to Extest, Bypass, or Highz.

Eliminates requirement to use the DisablePreprocessBuffers instruction when using PlayRecordOn/Off instructions in flash programming models.

Build 4246

Adds default to place unused scan devices in HIGHZ mode vs BYPASS mode.

Corrects problem reading DTS models from the commands list in ProScan.

Upgrades and corrects the ShowMe! debugger.

Build 4245Corrects problem when assigning “No Test” to JTAG Chains in cluster test applications
Build 4244

Adds debug capability to ProScan screen. See discussion related to debugging and setting guards in the help for the ProScan screen.

Generalizes translation capabilities for CadSoft Eagle style netlists.

Build 4243Upgrades ProScan screen: synchronizes presentations in splitter windows during single-stepping; enables Auto Detect button; corrects potential crash condition.
Build 4242Upgrades PADS POWER_PCB netlist translator to extract part information from *MISC* section.
Build 4241Corrects problem retaining new guards settings.
Build 4240

Ensures that a clock is developed for memory cluster tests where the clock pins are differential pairs declared in the BSDL file.

Corrects problem with settings for dual channel high speed onTAP USB cable so that full range of TCK rates is available.

Build 4239

Adds capability to include test setup messages, shown when loading or selecting an SVF file, with each SVF. To use, select an SVF file from list on Test screen and click the Test Setups / User Messages button.

Loads SVF file when accessing Test screen following test generation on the Development screen.

Build 4238Changes centered around settings on TestGen page plus various program corrections and upgrades.
Build 4235Adds provisions to allow running single-chain applications using onTAP USB cables when the serial number of the USB cable in the related adaptor file does not match the S/N of the cable in use. This condition previously required a user to reload an SVF file
Build 4234

Corrects possible crash condition when looping tests or running burn-in

Allows jumpers to be added for no-connect pins

Upgrades syntax check on Guards page

Adds syntax check to ensure that declared subroutines have a body

Corrects potential crash when selecting Save Project from the File menu

Corrects problem using hex notation X’ when passing constant values as arguments to subroutines

Build 4233

Upgrades handling of Jumpers so that jumper settings are implemented directly in a netlist when an application netlist is read by onTAP

Corrects test generation problem involving logic element circuits

Improves management of onTAP USB cable in test start-up situations, when a UUT’s power is cycled, and when a USB cable is disconnected / reconnected

Upgrades Development screen’s TestGen page so that test procedures may be refined by selecting specific TAP instructions or procedures. Test generation will proceed normally without changing any of the check box selections on the TestGen page.

Reduces clutter on the Settings page. Moves Adaptor file settings to the Cables menu pages from the Settings page. An onTAP USB cable-based adaptor file is created by default if an adaptor file doesn’t exist

Adds project notes access on the Projects page, enabling users to maintain notes about aspects of a project

Upgrades handling of GetKeyboardStr instruction to support the Cancel button so that Cancel results in a null string length

Build 4230

Drops need to have Microsoft .NET Framework installed when running onTAP. This was requirement had begun with build 4229.

Corrects problem that required program reloads when cycling power on boards having more than one JTAG chain.

Build 4227Adds capability to refine ShowMe! capture data for cluster test debug purposes.
Build 4226Includes adjustment for Parallel test option when using onTAP Network License Manager.
Build 4225

Introduces ShowMe!, a new tool for debugging cluster tests. ShowMe! Is accessible from the Debug menu and provides a spreadsheet-like view of drive and capture values at all pin groups, pins, and DTS program variables throughout a test. ShowMe! can be run with or without a test/program cable attached.

Allows the debug mode ‘Log TDO HEX Data’ to run and capture data with or without a test/program cable present.

Makes default status of JTAG devices ‘unsafe’ in Test Only Safe Circuit mode, unless the JTAG device’s reference designator is placed in the …project_settingssafe_devices_.txt list

Simplifies and improves controls on USB Cables dialog used to create adaptor files for USB cables.

Updates Browse control on Projects page

Adds text to scandata debug file showing failing pin names

Build 4221Ensures that BYPASS and not HIGHZ instructions are used in cluster tests
Build 4220

Add netlist translator support for Zuken CFF files

Adds safeguard when testing nets having JTAG pins and the associated JTAGdevice is in Bypass mode. These nets will not be tested by other JTAG pins on the nets unless the JTAG device in Bypass is listed in the safe_circuits_.txt file

Build 4219

Updates settings and presentation of scan pin assignments on the Cluster page

Adds new tests to quickly check the onTAP USB cable from the test screens and USB Cable settings page

Build 4218

Adds a Settings change log with an undo capability on the ProScan screen when using the Guards+Attibutes page. This provides a convenient way to make guards and attribute changes, compile, test, review results, and undo changes as required

Adds additional diagnostic information related to TAP test failures. Detailed bit information for instruction capture and IDCODE code responses is provided in diagnostic messages

Build 4217

Adjusts ProScan so that screen is updated only once after a recompile.

Includes Microsoft Visual Studio redistributable DLLs in installation package so that onTAP should run without the MS redistributable. However, if there are DLL complaints when loading onTAP, please run the MS redistributable at this link


Build 4211

Upgrades “Update Other Adaptors’ tool on USB Cables dialogue, allowing all adaptor files to be updated with USB port and TCK rate assignments.

Adds ‘drag-and-drop’ capability to reorder SVF files in SVF Files list on Manufacturing Test screen.

Build 4210Ensures correct use of Interconnect,Bypass and Interconnect,Bypass(NO-HIGHZ) instructions on TestGen page
Build 4209

Upgrades GenRad ICT translator

Adds Direct Drive, allowing programming of serial flash directly from USB cable leads, bypassing boundary scan

Upgrades handling of alternate IDCODES at run-time

Updates onTAP DLLs

Build 4206Updates run-time support for DTS models
Build 4205

Adds capability to accept alternate IDCODES for JTAG devices at run-time. Press F1 for Help on Test screen for details

Corrects problem where integer array expressions can be excluded in SVF files

Build 4204

Corrects diagnostic messages for %PIN: expressions for DTS models that use pin groups where individual pins are declared as EXTERNAL

Corrects screen text for Windows UI fonts and resolutions where text on the screen can be cropped

Build 4203Fixes program exception related to running cluster tests with multiple JTAG chains
Build 4200Improves asserting guards during cluster tests
Build 4198

Adds capability to directly run binary flash files. ( Check with technical support to see which flash devices have been tested.)

Reduces test execution times

Adds preventive code for potential program exceptions

Upgrades Netlist Merge tool providing capability for accepting user-edited merge_pins files. Adds debug trace file that shows sequence of merge steps

Adjusts screen settings for PCs in China

Build 4194Upgrades code related to serial flash programming models
Build 4193Corrects problem in DTS models when passing in values to subroutines and calling subroutines from subroutines
Build 4192Usability enhancements
Build 4191

Adds capability to write message strings with variables from within the ShowFail(message) instruction

Adds capability to run script-generated SVF files with updated scans based on varying bit string values

Build 4190Corrects problem updating pin register values in DTS models when running cluster tests in multi-chain applications
Build 4189

Corrects problem setting preload values for 1149.6 AC differential receivers when the pin type is bidirectional

Corrects problem setting guards from ProScan on bidirectional differential receiver pins.

Corrects problem related to option on Jumpers page to automatically add jumpers for IEEE 1149.6 testing of capacitively coupled devices. Extends capability so that in-line resistors are accounted for

Build 4187Upgrades User Defined script capabilities
Build 4186Adds capability to run Play/Record binary files in buffered mode, reducing run time and eliminating program latency while in the Run-Test/Idle state
Build 4184

Updates support for onTAP GPIO Serializer

Corrects test generation problem when pins from devices in multiple JTAG chains are used in cluster tests

Upgrades handling of unplug-plug events for onTAP USB cables

Build 4183

Adds support for AUG netlist format.

Corrects problem showing bit-string message values in user-defined scripts.

Build 4181Updates User Defined code.
Build 4179Ensures that pins are alternately selected to drive a net when the pins are joined by low-ohm resistors, providing each pin a chance to drive high and low multiple times.
Build 4178Allows for use of for-loops in User Defined tests.
Build 4177Updates Protel netlist translator
Build 4174Sets preload capture values for to opposite value of expected capture values.
Build 4173Updates 1149.6 related settings.
Build 4172Add preload provisions for 1149.6 sample instruction.
Build 4171Corrects problem related to incorrect test values in multi-chain applications for the vectors following the SAMPLE instruction for some configurations.
Build 4170Improves usability of ProScan graphical debug environment by adding advanced controls for search, pin level diagnostics, and ease of switching between and running tests.
Build 4166

Improves Reset operation of USB cable when Reset buttons are clicked and when calling Reset from the onTAP DLLs.

Adjusts diagnostic message for no-connect pins in the event of stuck-at faults.

Upgrades use of EXTEST_TRAIN instruction for 1149.6 AC testing.

Build 4165

Adds pin-wiggle capability in ProScan for 1149.6 AC coupled pins.

Upgrades Guards+Attributes tab in ProScan to facilitate setting guards, attributes, recompiling, and rerunning tests from within ProScan.

Corrects problem showing test messages for multi-chain applications.

Adjusts FabMaster netlist translator code.

Build 4164Corrects DTS test generation where EXTERNAL pin declarations are used when large numbers of cells with common control cells are present.
Build 4163Adds screen to view onTAP Network License Manager’s server screen.
Build 4162

Updates for Play/Record feature used when loading configuration files.

Updates for licensing and onTAP Network License Manager.

Build 4161Corrects problem with IDCODE tests resulting from millisecond delay settings in multi-chain tests or when specified on the Settings page.
Build 4160

Includes updates for programming Lattice FPGAs.

Upgrades differential pair testing. Reads port groupings of differential pair pins in BSDL files and accounts for all positive and negative side pins using BSDL files and netlist.

Build 4158

Adds Play/Record feature for SVF program configuration files. Play/Record converts SVF files to binary, allowing faster programming. Play / Record can be enabled from the Cables menu for specific SVF files.

Ensures that guard constraints in the Browse Circuit view are updated when a guard condition is changed the Vector view

Build 4157Improves stability in ProScan debugging environment
Build 4156Enables manual input of text in the License Request Folder Edit box on the Help About page.
Build 4155Statically links Windows DLLs to enable that user’s have the correct DLLs
Build 4153Corrects potential false failures in multi-chain applications
Build 4152Ads stability when generating tests for some multi-JTAG chain applications
Build 4151

Corrects problem writing failure reports from Mfg test screen when Operator, Serial Number, and Unit Type text strings are entered.

Adds pin-wiggling capability on Nets screen and ProScan for the Xilinx USB cable

Build 4150Adds code for Xilinx USB Platform Cable support (Beta).
Build 4149Adds SAMPLE/PRELOAD instruction as a default in first cluster test scan prior to EXTEST instruction.
Build 4148

Corrects test generation for circuits with shared control cells to ensure that only one driver on a net is active at one time.

Moves license file, LogicPinMaps and other files within the onTAP folder to the c:Flynn Systems CorponTAP folder, in order to avoid write protected folders within the c:Program Files folder. The default installation folder is still c:Program FilesonTAP.

Adds code in preparation of support for the Xilinx USB Cable II.

Build 4146Improves coverage for handling guards when current limiting is enabled
Build 4145

Corrects problem with current-limiting option.

Corrects problem writing serial-number-specific files when testing from the Manufacturing Test screen.

Build 4143

Adds netlist translator support for IPL Wirelist netlists

Includes adjustment for the current limiting option

Build 4142Changes the Scan switch factor on the Settings page to a current limiting switch factor (CLSF). Values greater than one limit the total number of pins that can be active at one time during the opens, stuck-at, and pull resistor tests.
Build 4141Improves handling of edits to attributes and pin-map model assignments on the non-Scan page.
Build 4140

Adjusts ground bounce switch factor operation for pull-up/down tests.

Introduces option to add vectors and extend fault coverage in applications where pins share common tri-state control cells. The option is controlled by the “Alternate drive on pins having common control cells” check box on the settings page and the default setting is enabled.

Ensures that all eligible pins alternate drive on nets having multiple scan pins.

Corrects problem showing all LogicPinMap models on the non-Scan page.

Build 4139Ease-of-use adjusments
Build 4138Revises and extends the manner in which the Save Test Reports option works on the Mfg Test screen
Build 4137

Improves operation of JTAG Chain Auto Detect.

Adds support for ground debounce switch factor for pull-up/down tests.

Adds protection for test settings in the ProScan environment.

Build 4136

Adds support for return instruction in DTS model subroutines.

Updates and expands on-line help.

Build 4135

Adds support for use of local variables within subroutines.

Adds corrections for test status messages when stopping a test.

Build 4134Upgrades test vector generation for ground debounce settings greater than one.
Build 4133Adds safeguards to prevent problems accessing dot fail files when running onTAP DLLs.
Build 4132

Includes inductors in tests solutions and treats inductors as low impedance resistors.

Corrects problem with test generation involving low impedance devices.

Build 4131Additional corrections made for Test Status text as well as shorts test coverage in applications having bus transceiver models
Build 4130Corrects test message shown in the Test Status column of the Test screens when the Retries on Fail value is greater than zero and a test failure occurs when multiple SVF files are selected.
Build 4129Adds loopback cable test, in the Cables menu, for the dual channel 30Mhz cable and restores loopback test for the single channel 6Mhz cable.
Build 4128Provides additional correction for transceiver management during test generation

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