June 12, 2017

Finding Faults with the Test Access Port (TAP)

Flynn Systems Corporation

JTAGOnce a board developer passes along the new board and all related files and procedures to a test developer, the boundary scan test process can begin. We recommend including the TAP Integrity Test at the beginning of your interconnect test because the TAP contains pins associated with the test access controller, e g., the TAP CONNECT JTAG Controller. The TAP Integrity Test is created automatically with the TAP access controller manipulating pins to perform the following tests:

  • Instruction Capture
  • Instruction Register Length
  • Bypass

(Additionally, the Boundary Register Length may be added to the TAP Integrity Test.)

A successful TAP Integrity Test shows:

  • the access controller is working properly
  • the scan chain is operable
  • the scan path is unimpaired

While most TAP tests pass, failures can occur. For example, an Instruction Register Length error or an IDCODE error can be indicative of a problem with one or more of the BSDL files used in the project where the BSDL files do not match their respective devices. One solution is the obvious: check that the correct BSDL files are being used. If the BSDL files are correct and the most current, your software tool should provide some troubleshooting options. For example, onTAP would suggest options such as:

  • check the TAP CONNECT JTAG Controller (access controller) to assure Vref is available from either the UUT or from the Controller’s internal voltage source.
  • verify the Controller port assignments are correct
  • verify the JTAG chain or chains are properly defined
  • check that any TRST pins are held high and that any compliance pins declared in the BSDL files are held at the indicated values.

When a failure occurs, ideally your software tool should provide you with diagnostic messages to the pin level. In the figure below, we forced a fault when running the TAP Integrity Test using the TAP CONNECT JTAG Controller. onTAP’s diagnostic message tells us the location, the device and the pin where the chain is broken and provides troubleshooting suggestions. In the image below, only TCK, TMS, optionally TRST, and TDO are used for the Instruction Capture Test.

When a TAP Integrity Test passes, users can view the four elements of that test, as well as the chain and chain order.  Now that you know your test access controller is operational, the interconnect test is ready to be developed.

For more information about the TAP, please view the video on our site: The JTAG TAP Controller Tutorial. Or, call us—we’re always happy to answer any boundary scan questions you may have!

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Flynn Systems Corporation

June 12, 2017