Design for Testability, often referred to as DFT, is a critical part of developing a new board. Here’s a link to a terrific class lecture from University of Maryland if you’re interested in seeing a well represented academic presentation of such an important topic.
Why is DFT so important? Risk and cost reduction.
As boards become increasingly more complex, they become increasingly more expensive to produce, and they become more difficult to test to ensure they are functioning properly. Metal-to-metal connections are all but eliminated, and other test methods can’t verify the interconnectivity of the devices. This, of course, starts with multi-layered boards, the introduction of BGA FPGA’s and processors, multiple memory devices, Systems on Chip, PCI/PCIe buses, all coupled with a wide variety of other discrete components that voraciously consume valuable board real estate. Prior to laying out the board, it is critical that the engineering team decide on the test strategy that will be employed during prototyping and manufacturing. Of course, our preference is to include boundary scan software / JTAG tools for JTAG testing. Regardless of the strategy and test methods, it is imperative to develop a test strategy that supports the project “cradle to grave.”
Here’s why, in small part. A DFT guideline that includes boundary scan testing / JTAG testing can help: Xilinx and Altera, to name a couple companies, are issuing FPGA’s that cost in the tens of thousands of dollars for each device. These substantially expensive devices, while incredibly powerful, have no direct test access once installed on a board. They may be able to be removed and tested in stand-alone test configurations, but aside from functional test, there is no really good way to test the device as part of the overall design and ensure it works as intended. And, if functional test is the go/no-go test, there is high risk of frying a device that could cost as much as a good used car!
Enter design for testability. By laying a good foundation for the testability of the board, you can ensure that your test access and test methods are accounted for in the design and test process. This supports the next phase of production, helps reduce the risk of frying components on the board, and helps move the production process along with greater efficiency. Some areas of consideration for DFT include checking to ensure that test pins aren’t tied to ground, and double checking specs for compatibility between devices. Also very important is verifying devices are able to be used in the design. Believe it or not, we’ve seen issues where certain devices are entered into application mode, rendering test mode completely ineffective. In these types of situations, it’s taken lots of back and forth with board designers and product manufacturers to troubleshoot the problem.
Good DFT practices will save lots of time at the outset of the project, and will pay dividends in the future as the board design moves from prototyping to production and finally into service. With good DFT practices at the outset of the project, FAE’s can help customers years later knowing that the board design includes testability functionality to help diagnose problems. Talk to your friendly boundary scan representative to learn more about how to factor this JTAG testing technology into your DFT practices.
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