While not all boundary scan terminology is contained in the guide, there are enough terms to at least acquaint you with some of the most commonly used expressions.
BIST:
Built-In Self-Test, sometimes controllable via boundary scan
BOARD NETLIST:
Files that show the connections between devices on a circuit board and the probe access to circuit nets. Many formats are available, including PADS. CADENCE, EDIF, ALLEGRO, etc.
BOUNDARY REGISTER:
A network of register cells linking the TDI and TDO TAP pins. This network provides access to package pins and to system circuits.
BOUNDARY SCAN:
A test and access method for electronic devices based on IEEE. Std 1149.1a –2001 specification. Boundary Scan employs scan registers which may operate in system or test mode at each system pin. The boundary scan circuit is controlled by a test access port (TAP) which has four required pins and one optional pin (see TAP).
BSDL:
Boundary Scan Description Language is based on the IEEE 1149.1 standard. BSDL files provide a hardware description language of boundary scan circuits, and most contain the filename extension .bsd or .bsdl. BSDL is a subset of VHDL (Verilog Hardware Description Language).
BYPASS:
A boundary scan instruction that allows test data to go through a device and to bypass the boundary register.
CHAINS:
Configuration of multiple boundary scan devices.
CLUSTER TEST:
An onTAP method of applying test vectors through JTAG-capable devices to non-JTAG devices.
DISABLE:
An in-circuit test technique of electrically isolating a device under test (DUT) by applying input signal patterns that turn off the devices that interact with the DUT.
EDIF NETLIST:
Electronic Data Interchange Format, is a netlist for a circuit within a device or between devices.
EXTEST:
A boundary scan instruction for interconnect test.
GUARDS:
Used with constraints, such as forcing a value on a net, to “guard” or limit interaction between boundary scan and non-boundary scan circuits.
HIGHZ:
Output high impedance condition.
ICT:
In-Circuit Testing is a type of automatic test equipment in digital electronic board manufacturing. ICT accesses digital devices on a PCB through a bed-of-nails test fixture. This access allows ICT to test one device at a time while disabling any devices that interact and might cause test conflicts with the device under test.
IEEE 1149.1:
The standards established by the Joint Action Test Group (JTAG) for boundary scan architecture that incorporates TAP for boundary scan testing of complex ICs. As a whole, these standards have become synonymous with “JTAG test” and “boundary scan test” (http://www.ieee.org/index.html).
IEEE 1149.6:
An additional IEEE standard that provides for A/C testing (http://www.ieee.org/index.html).
INTERCONNECT TEST:
A boundary scan test between multiple devices that uses scan patterns, typically Wagner patterns, to check pin to pin connections and shorts.
INTEST:
An instruction that allows parallel test vectors to functionally test through a device and to be transported via boundary scan.
ISP:
In System Programming is a technique of configuring programmable logic devices via boundary scan.
JTAG:
The Joint Test Action Group was a test standards committee that established the current IEEE 1149.1 standards for boundary scan architecture, incorporating the TAP (Test Access Port). The acronym is now synonymous with the group’s output. The terms “JTAG”, “boundary scan” and “IEEE 1149.1” are used interchangeably.
JUMPERS:
When circuit elements, such as resistors and bus transceivers, residing between boundary scan pins are made transparent so that the boundary scan pins are effectively joined together.
onTAP:
Flynn Systems’ Automatic Test Generation suite of Boundary Scan tools.
TAP:
Test Access Port. Each boundary scan device has a TAP that contains the TAP pins, state machine controller circuit, boundary register, and optional BIST and ISP circuits. All conform to the IEEE 1149.1 standards (http://fiona.dmcs.pl/~cmaj/JTAG/JTAG_IEEE-Std-1149.1-2001.pdf)
TAP pins are:
TDI (test data in)
TDO (test data out)
TMS (test mode select)
TCK (test clock)
and optionally
TRST (test reset)
TEST PATTERN:
A sequence of applied input values and expected output values related to a device’s I/O pins over a series of test steps.
Transparent Devices:
Circuit elements such as resistors and bus transceivers that reside between boundary scan pins may be made “transparent” so that the boundary-scan pins are effectively joined or “jumpered” together.
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